초록 ▼

A method includes determining a need to perform a learn cycle on a battery in a processing module of an information handling system, detecting a learn cycle in progress on another battery in another processing module of the information handling system, and postponing the learn cycle on the battery i

A method includes determining a need to perform a learn cycle on a battery in a processing module of an information handling system, detecting a learn cycle in progress on another battery in another processing module of the information handling system, and postponing the learn cycle on the battery in response to detecting the learn cycle on the other battery.

대표청구항 ▼

1. A method comprising: determining, by a first baseboard management controller of a first processing module, a need for initiating a first learn cycle on a first battery of the first processing module, wherein the first battery, the first baseboard management controller and the first processing mod

1. A method comprising: determining, by a first baseboard management controller of a first processing module, a need for initiating a first learn cycle on a first battery of the first processing module, wherein the first battery, the first baseboard management controller and the first processing module are located within an information handling system;detecting, by the first baseboard management controller, that a second learn cycle is in progress on a second battery of a second processing module, wherein detecting that the second learn cycle is in progress includes detecting, by the first baseboard management controller, an indication that the second learn cycle is in progress, wherein the second battery and the second processing module are located within the information handling system; andpostponing the first learn cycle, in response to detecting that the second learn cycle is in progress. 2. The method of claim 1, further comprising: detecting, by the first baseboard management controller, that the second learn cycle has completed; andinitiating the first learn cycle, in response to detecting that the second learn cycle has completed. 3. The method of claim 2, further comprising: providing an indication that the first learn cycle is complete, in response to successful performance of the first learn cycle. 4. The method of claim 1, further comprising: generating, by a second baseboard management controller, the indication that the second learn cycle is in progress; andproviding, by the second baseboard management controller, the indication that the second learn cycle is in progress. 5. The method of claim 4, wherein providing the indication further comprises: sending status information on a communication network accessible to the first baseboard management controller and to the second baseboard management controller. 6. The method of claim 5, wherein the communication network is an inter-baseboard management controller communication link. 7. The method of claim 4, wherein determining the need for initiating the first learn cycle comprises: receiving a command to perform the first learn cycle from a system management controller. 8. The method of claim 4, wherein determining the need for initiating the first learn cycle comprises: retrieving a predetermined learn time of the first learn cycle;comparing the predetermined learn time with a current time; anddetermining that the current time is later than the predetermined learn time of the first learn cycle. 9. A first processor module comprising: a first battery; anda first baseboard management controller, the first baseboard management controller configured to: determine a need to initiate a first learn cycle on the first battery of the first processor module by receiving a command to perform the first learn cycle from a system management controller;detect that a second learn cycle is in progress on a second battery of a second processor module;postpone the first learn cycle, in response to detecting that the second learn cycle is in progress;detect that the second learn cycle is complete; andinitiate the first learn cycle. 10. The first processor module of claim 9, wherein the first baseboard management controller detects that the second learn cycle is in progress by detecting an indication that the second learn cycle is in progress generated by a second baseboard management controller of the second processor module. 11. The first processor module of claim 10, wherein an inter-baseboard management controller communication link couples the first baseboard management controller and the second baseboard management controller, and first baseboard management controller receives the indication that the second learn cycle is in progress from the second baseboard management controller through the inter-baseboard management controller communication link. 12. The first processor module of claim 9, wherein the first baseboard management controller is coupled to a memory location accessible by a second baseboard management controller of the second processor module, and the first baseboard management controller detects that a second learn cycle is in progress by monitoring the memory location for a value written to the memory location by the second baseboard management controller. 13. The first processor module of claim 9, wherein: in determining the need to initiate the first learn cycle, the first baseboard management controller is further configured to: retrieve a predetermined learn time of the first learn cycle;compare the predetermined learn time with a current time; anddetermine that the current time is later than the predetermined learn time of the first learn cycle. 14. The first processor module of claim 9, wherein: in determining the need to initiate the first learn cycle, the first baseboard management controller is further configured to: retrieve a stored battery serial number;retrieve a first battery serial number from the first battery;compare the stored battery serial number to the first battery serial number;select a learn time for the first battery, in response to the comparing;compare the learn time with a current time; anddetermine that the current time is later than the learn time. 15. The first processor module of claim 9, wherein the first baseboard management controller is further configured to: provide an indication the first learn cycle is complete, in response to successful completion of the first learn cycle. 16. A power supply device comprising: an internal communication network;a first battery module;a second battery module;a first baseboard management controller coupled to the internal communication network and the first battery module, and configured to determine a need for performing a first battery learn cycle; anda second baseboard management controller coupled to the internal communication network and the second battery module, the second baseboard management controller configured to generate an indication that a battery learn cycle is in progress, wherein the first baseboard management controller is configured to receive the indication that the second battery learn cycle is in progress, and in response, delay the first battery learn cycle. 17. The network storage device of claim 16, further comprising: a first storage processor comprising the first baseboard management controller and the first battery module; anda second storage processor comprising the second baseboard management controller and the second battery module. 18. The network storage device of claim 16, further comprising: a chassis management controller coupled to the internal communication network, the chassis management controller operable to: receive the indication from the second baseboard management controller; andprovide the indication to the first baseboard management controller. 19. The network storage device of claim 16, wherein the first battery module comprises first battery cells, first power regulation circuitry, first charging circuitry, and first control circuitry, and wherein the second battery module comprises second battery cells, second power regulation circuitry, second charging circuitry, and second control circuitry.