최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0831530 (2013-03-14) |
등록번호 | US-10020321 (2018-07-10) |
발명자 / 주소 |
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출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 588 |
A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode
A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.
1. A cross-coupled transistor circuit, comprising: a first PMOS transistor having a gate electrode extending along a first line;a first NMOS transistor having a gate electrode extending along a second line;a second PMOS transistor having a gate electrode extending along the second line;a second NMOS
1. A cross-coupled transistor circuit, comprising: a first PMOS transistor having a gate electrode extending along a first line;a first NMOS transistor having a gate electrode extending along a second line;a second PMOS transistor having a gate electrode extending along the second line;a second NMOS transistor having a gate electrode extending along the first line,wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected together,wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected together,wherein each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node,wherein the diffusion terminal of the first PMOS transistor is physically separated from the diffusion terminal of the second NMOS transistor,wherein the diffusion terminal of the second PMOS transistor is physically separated from the diffusion terminal of the first NMOS transistor. 2. The cross-coupled transistor circuit as recited in claim 1, wherein the gate electrode of the first PMOS transistor is formed as part of a first linear-shaped conductive structure, the first linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the first PMOS transistor toward the second NMOS transistor. 3. The cross-coupled transistor circuit as recited in claim 2, wherein the gate electrode of the first NMOS transistor is formed as part of a second linear-shaped conductive structure, the second linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the first NMOS transistor toward the second PMOS transistor. 4. The cross-coupled transistor circuit as recited in claim 3, wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected together through a first set of electrical conductors that includes a first conductive structure physically contacting a part of the inner extension portion of the first linear-shaped conductive structure and a second conductive structure physically contacting a part of the inner extension portion of the second linear-shaped conductive structure. 5. The cross-coupled transistor circuit as recited in claim 4, wherein the first set of electrical conductors includes a single interconnect level structure that physically connects to both the first conductive structure and the second conductive structure. 6. The cross-coupled transistor circuit as recited in claim 4, wherein the first set of electrical conductors includes multiple interconnect level structures, wherein one of the multiple interconnect level structures physically connects to the first conductive structure, and wherein one of the multiple interconnect level structures physically connects to the second conductive structure. 7. The cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the second PMOS transistor is formed as part of a third linear-shaped conductive structure, the third linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the second PMOS transistor toward the first NMOS transistor. 8. The cross-coupled transistor circuit as recited in claim 7, wherein the gate electrode of the second NMOS transistor is formed as part of a fourth linear-shaped conductive structure, the fourth linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the second NMOS transistor toward the first PMOS transistor. 9. The cross-coupled transistor circuit as recited in claim 8, wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected together through a second set of electrical conductors that includes a third conductive structure physically contacting a part of the inner extension portion of the third linear-shaped conductive structure and a fourth conductive structure physically contacting a part of the inner extension portion of the fourth linear-shaped conductive structure. 10. The cross-coupled transistor circuit as recited in claim 9, wherein the second set of electrical conductors includes a single interconnect level structure that physically connects to both the third conductive structure and the fourth conductive structure. 11. The cross-coupled transistor circuit as recited in claim 9, wherein the second set of electrical conductors includes multiple interconnect level structures, wherein one of the multiple interconnect level structures physically connects to the third conductive structure, and wherein one of the multiple interconnect level structures physically connects to the fourth conductive structure. 12. The cross-coupled transistor circuit as recited in claim 1, wherein the diffusion terminal of the first PMOS transistor that is connected to the common output node and the diffusion terminal of the second PMOS transistor that is connected to the common output node are parts of a first shared diffusion terminal, and wherein the diffusion terminal of the first NMOS transistor that is connected to the common output node and the diffusion terminal of the second NMOS transistor that is connected to the common output node are parts of a second shared diffusion terminal. 13. The cross-coupled transistor circuit as recited in claim 12, further comprising: a first diffusion contact connected to the first shared diffusion terminal; anda second diffusion contact connected to the second shared diffusion terminal. 14. The cross-coupled transistor circuit as recited in claim 13, further comprising: a single interconnect level structure that physically connects to both the first diffusion contact and the second diffusion contact. 15. The cross-coupled transistor circuit as recited in claim 13, further comprising: a first interconnect level structure that physically connects to the first diffusion contact; anda second interconnect level structure that physically connects to the second diffusion contact. 16. The cross-coupled transistor circuit as recited in claim 15, wherein the first and second interconnect level structures are located in different interconnect levels. 17. The cross-coupled transistor circuit as recited in claim 15, wherein the first and second interconnect level structures are located in a same interconnect level. 18. A method for manufacturing a semiconductor device, comprising: forming a gate electrode of a first PMOS transistor to extend along a first line;forming a gate electrode of a first NMOS transistor to extend along a second line;forming a gate electrode of a second PMOS transistor to extend along the second line;forming a gate electrode of a second NMOS transistor to extend along the first line;electrically connecting the gate electrodes of the first PMOS transistor and the first NMOS transistor together;electrically connecting the gate electrodes of the second PMOS transistor and the second NMOS transistor together;electrically connecting a diffusion terminal of the first PMOS transistor to a common output node;electrically connecting a diffusion terminal of the first NMOS transistor to the common output node;electrically connecting a diffusion terminal of the second PMOS transistor to the common output node; andelectrically connecting a diffusion terminal of the second NMOS transistor to the common node,wherein the diffusion terminal of the first PMOS transistor is physically separate from the diffusion terminal of the second NMOS transistor,wherein the diffusion terminal of the second PMOS transistor is physically separate from the diffusion terminal of the first NMOS transistor. 19. The method for manufacturing a semiconductor device as recited in claim 18, wherein the gate electrode of the first PMOS transistor is formed as part of a first linear-shaped conductive structure, the first linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the first PMOS transistor toward the second NMOS transistor. 20. The method for manufacturing a semiconductor device as recited in claim 19, wherein the gate electrode of the first NMOS transistor is formed as part of a second linear-shaped conductive structure, the second linear-shaped conductive structure including an inner extension portion extending away from the gate electrode of the first NMOS transistor toward the second PMOS transistor. 21. A cross-coupled transistor circuit, comprising: a first transistor of a first transistor type formed in part by a first gate electrode structure, the first gate electrode structure shaped to extend in a substantially straight manner in a first direction substantially parallel to an underlying substrate;a second transistor of the first transistor type formed in part by a second gate electrode structure, the second gate electrode structure shaped to extend in a substantially straight manner in the first direction substantially parallel to the underlying substrate;a first transistor of a second transistor type formed in part by a third gate electrode structure, the third gate electrode structure shaped to extend in a substantially straight manner in the first direction substantially parallel to the underlying substrate;a second transistor of the second transistor type formed in part by a fourth gate electrode structure, the fourth gate electrode structure shaped to extend in a substantially straight manner in the first direction substantially parallel to the underlying substrate; andan interconnect structure shaped to extend in a substantially straight manner in the first direction substantially parallel to the underlying substrate, the interconnect structure substantially centered between the first gate electrode structure and the second gate electrode structure, the interconnect structure substantially centered between the third gate electrode structure and the fourth gate electrode structure. 22. The cross-coupled transistor circuit as recited in claim 21, wherein the interconnect structure is electrically connected to a diffusion terminal of the first transistor of the first transistor type, and wherein the interconnect structure is electrically connected to a diffusion terminal of the second transistor of the first transistor type, and wherein the interconnect structure is electrically connected to a diffusion terminal of the first transistor of the second transistor type, and wherein the interconnect structure is electrically connected to a diffusion terminal of the second transistor of the second transistor type. 23. A semiconductor chip, comprising: a first transistor of a first transistor type;a second transistor of the first transistor type;a first transistor of a second transistor type;a second transistor of the second transistor type,the first transistor of the first transistor type having a gate electrode electrically connected to a gate electrode of the first transistor of the second transistor type,the second transistor of the first transistor type having a gate electrode electrically connected to a gate electrode of the second transistor of the second transistor type,each of the first transistor of the first transistor type and the second transistor of the first transistor type and the first transistor of the second transistor type and the second transistor of the second transistor type having a respective diffusion terminal electrically connected together,the gate electrode of the first transistor of the first transistor type co-aligned with the gate electrode of the second transistor of the second transistor type,diffusion terminals of the first and second transistors of the first transistor type separated from diffusion terminals of the first and second transistors of the second transistor type. 24. A cross-coupled transistor circuit, comprising: a first transistor having a gate electrode extending along a first line;a second transistor having a gate electrode extending along a second line;a third transistor having a gate electrode extending along the second line;a fourth transistor having a gate electrode extending along the first line,wherein the gate electrodes of the first and third transistors are electrically connected together,wherein the gate electrodes of the second and fourth transistors are electrically connected together,wherein each of the first, second, third, and fourth transistors has a respective diffusion terminal electrically connected together. 25. The cross-coupled transistor circuit as recited in claim 24, wherein the gate electrodes of the first, second, third, and fourth transistors are formed as parts of a plurality of conductive structures, wherein each of the plurality of conductive structures respectively has a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the plurality of conductive structures co-planar with each other,each of the plurality of conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the plurality of conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the plurality of conductive structures is substantially straight,wherein the second edge of each of the plurality of conductive structures is substantially straight,each of the plurality of conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the plurality of conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the plurality of conductive structures. 26. The cross-coupled transistor circuit as recited in claim 25, wherein the width of each of the plurality of conductive structures is less than 45 nanometers, the region having a size of about 965 nanometers as measured in the second direction, each of the plurality of conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the plurality of conductive structures is substantially equal to a first pitch. 27. The cross-coupled transistor circuit as recited in claim 26, wherein the first pitch is less than or equal to about 193 nanometers. 28. A cross-coupled transistor circuit, comprising: a first conductive structure having a substantially rectangular shape defined by a length measured along a lengthwise centerline and a width measured perpendicular to its lengthwise centerline, the first conductive structure oriented to have its lengthwise centerline oriented in a first direction, the first conductive structure forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type; anda second conductive structure having a substantially rectangular shape defined by a length measured along a lengthwise centerline and a width measured perpendicular to its lengthwise centerline, the second conductive structure oriented to have its lengthwise centerline oriented in the first direction, the second conductive structure forming both a gate electrode of a second transistor of the first transistor type and a gate electrode of a second transistor of the second transistor type,the first transistor of the first transistor type formed in part by a first diffusion region,the second transistor of the first transistor type formed in part by a second diffusion region,the first transistor of the second transistor type formed in part by a third diffusion region,the second transistor of the second transistor type formed in part by a fourth diffusion region, andeach of the first diffusion region and the second diffusion region and the third diffusion region and the fourth diffusion region electrically connected to a common node. 29. The cross-coupled transistor circuit as recited in claim 28, wherein the first diffusion region and the second diffusion region are physically connected to each other. 30. The cross-coupled transistor circuit as recited in claim 29, wherein the third diffusion region and the fourth diffusion region are physically connected to each other. 31. The cross-coupled transistor circuit as recited in claim 30, further comprising: an interconnect conductive structure including a segment oriented to extend in the first direction from a location over an intersection of the first diffusion region and the second diffusion region to a location over an intersection of the third diffusion region and the fourth diffusion region;a first via conductive structure formed to extend vertically through the semiconductor chip from the segment of the interconnect conductive structure to the intersection of the first diffusion region and the second diffusion region; anda second via conductive structure formed to extend vertically through the semiconductor chip from the segment of the interconnect conductive structure to the intersection of the third diffusion region and the fourth diffusion region. 32. The cross-coupled transistor circuit as recited in claim 28, wherein a region between the first conductive structure and the second conductive structure does not include another transistor gate-forming conductive structure. 33. The cross-coupled transistor circuit as recited in claim 28, wherein a distance measured between the lengthwise centerline of the first conductive structure and the lengthwise centerline of the second conductive structure and perpendicular to both the lengthwise centerline of the first conductive structure and the lengthwise centerline of the second conductive structure is equal to an integer multiple of a gate electrode pitch. 34. The cross-coupled transistor circuit as recited in claim 28, wherein the first transistor of the first transistor type is formed in part by a fifth diffusion region, and wherein the second transistor of the second transistor type is formed in part by a sixth diffusion region, and wherein the fifth diffusion region and the sixth diffusion region are electrically connected to each other. 35. The cross-coupled transistor circuit as recited in claim 34, wherein the second transistor of the first transistor type is formed in part by a seventh diffusion region, and wherein the first transistor of the second transistor type is formed in part by an eighth diffusion region, and wherein the seventh diffusion region and the eighth diffusion region are electrically connected to each other. 36. The cross-coupled transistor circuit as recited in claim 28, wherein the width of the first conductive structure is substantially equal to the width of the second conductive structure. 37. The cross-coupled transistor circuit as recited in claim 36, wherein the length of the first conductive structure is substantially equal to the length of the second conductive structure. 38. The cross-coupled transistor circuit as recited in claim 37, wherein a first end of the first conductive structure is substantially aligned with a first end of the second conductive structure. 39. A semiconductor chip, comprising: a first conductive structure having a substantially rectangular shape, the first conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type;a second conductive structure having a substantially rectangular shape, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type;a third conductive structure having a substantially rectangular shape, the third conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type;a fourth conductive structure having a substantially rectangular shape, the fourth conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type,wherein the first and third conductive structures are positioned along a same line extending in a first direction,wherein the second and fourth conductive structures are positioned along a same line extending in the first direction; andan interconnect conductive structure including at least two segments oriented perpendicular to each other, wherein the second and third conductive structures are electrically connected to each other through the interconnect conductive structure. 40. The semiconductor chip as recited in claim 39, wherein the interconnect conductive structure includes a first segment extending linearly in a second direction perpendicular to the first direction and a second segment extending from the first segment in the first direction and a third segment extending from the second segment in the second direction. 41. The semiconductor chip as recited in claim 40, further comprising: a first contact structure extending between the second conductive structure and the first segment of the interconnect conductive structure; anda second contact structure extending between the third conductive structure and the third segment of the interconnect conductive structure. 42. A semiconductor chip, comprising: a first conductive structure forming gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type;a second conductive structure forming gate electrodes of a second transistor of the first transistor type and a second transistor of the second transistor type; anda third conductive structure positioned between the first conductive structure and the second conductive structure, the third conductive structure electrically connecting a shared diffusion terminal of the first and second transistors of the first transistor type to a shared diffusion terminal of the first and second transistors of the second transistor type. 43. A semiconductor chip as recited in claim 42, wherein the first conductive structure is linear-shaped. 44. A semiconductor chip as recited in claim 43, wherein the second conductive structure is linear-shaped. 45. A semiconductor chip as recited in claim 44, wherein the third conductive structure is linear-shaped. 46. A semiconductor chip as recited in claim 45, wherein the third conductive structure is formed within an interconnect level located above a gate electrode level. 47. A semiconductor chip as recited in claim 45, wherein the third conductive structure is substantially centered between the first and second conductive structures.
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