Metal silicide, metal germanide, methods for making the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/45
C23C-016/06
C23C-016/455
C23C-016/40
H01L-021/285
H01L-021/324
H01L-021/3215
H01L-029/78
H01L-029/66
H01L-029/49
출원번호
US-0492892
(2017-04-20)
등록번호
US-10043880
(2018-08-07)
발명자
/ 주소
Pore, Viljami J.
Haukka, Suvi P.
Blomberg, Tom E.
Tois, Eva E.
출원인 / 주소
ASM INTERNATIONAL N.V.
대리인 / 주소
Knobbe, Martens, Olson & Bear LLP
인용정보
피인용 횟수 :
0인용 특허 :
185
초록▼
In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer.
In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.
대표청구항▼
1. A method for depositing an elemental cobalt (Co) thin film, the method comprising: providing a substrate comprising a 300 mm wafer in a reaction space of a flow type reactor, wherein the substrate comprises a silicon surface;carrying out one or more deposition cycles at a growth temperature of le
1. A method for depositing an elemental cobalt (Co) thin film, the method comprising: providing a substrate comprising a 300 mm wafer in a reaction space of a flow type reactor, wherein the substrate comprises a silicon surface;carrying out one or more deposition cycles at a growth temperature of less than about 400° C., the deposition cycle comprising:contacting the silicon surface of the substrate with a first vapor phase metal precursor comprising cobalt;removing excess first vapor phase metal precursor from the reaction space;contacting the substrate comprising the silicon surface and the cobalt with a second vapor phase reactant such that it reacts with the first vapor phase metal precursor to form elemental cobalt (Co);wherein the elemental cobalt (Co) thin film is deposited directly on the silicon surface of the substrate;subsequently depositing a thin film comprising a dopant over the elemental cobalt (Co) thin film; andannealing the substrate comprising the elemental cobalt (Co) thin film and the thin film comprising the dopant to form a doped cobalt silicide layer. 2. The method of claim 1, wherein the first vapor phase metal precursor is a metal compound in which the metal is bound or coordinated to oxygen, nitrogen, carbon or a combination thereof. 3. The method of claim 1, wherein the first vapor phase metal precursor is an organic compound. 4. The method of claim 3, wherein the first vapor phase metal precursor is a betadiketonate, betadiketiminato compounds, amidinate compounds, aminoalkoxide, ketoiminate or cyclopentadienyl compound. 5. The method of claim 3, wherein the first vapor phase metal precursor is a cyclopentadienyl cobalt compound. 6. The method of claim 3, wherein the first vapor phase metal precursor is a compound with the formula X(acac)y, where X is cobalt and y is between 2 and 3. 7. The method of claim 3, wherein the first vapor phase metal precursor is a compound with the formula X(thd)y, where X is cobalt, y is between 2 and 3 and thd is 2,2,6,6-tetramethyl-3,5-heptanedionato. 8. The method of claim 1, wherein the method is an atomic layer deposition (ALD) method. 9. The method of claim 8, wherein the ALD method comprises alternately and sequentially contacting the substrate with the first vapor phase metal precursor and the second vapor phase reactant. 10. The method of claim 1, wherein the growth temperature is less than about 200° C. 11. The method of claim 1, wherein the first vapor phase metal precursor is pulsed into the reaction space for from about 0.3 to 3 seconds. 12. The method of claim 1, wherein the dopant is a metal. 13. The method of claim 12, wherein the dopant is platinum. 14. The method of claim 1, wherein the dopant content in the doped cobalt silicide layer as a percentage of the overall metal content is about 0-10%.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (185)
Sneh Ofer ; Galewski Carl J., Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition.
Hadyn N. G. Wadley ; Xiaowang Zhou ; Junjie Quan, Apparatus and method for intra-layer modulation of the material deposition and assist beam and the multilayer structure produced therefrom.
Jin Sungho ; Klemmer Timothy J. ; Tiefel ; deceased Thomas Henry ; Van Dover Robert Bruce ; Zhu Wei, Article comprising anisotropic Co-Fe-Cr-N soft magnetic thin films.
Frijlink Peter M. (Crosne FRX), Device comprising a flat susceptor rotating parallel to a reference surface about a shift perpendicular to this surface.
Kirlin Peter S. ; Summerfelt Scott R. ; McIntryre Paul, Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same.
Lee Woo-Hyeong ; Manchanda Lalita, Electronic components with doped metal oxide dielectric materials and a process for making electronic components with do.
Yu, Bin; Wu, David, Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation.
Bowers Wayne E. (Clearwater FL) Sprague Barry N. (West Haven CT), Gasoline additives and gasoline containing soluble platinum group metal compounds and use in internal combustion engines.
Park In-seon,KRX ; Kim Yeong-kwan,KRX ; Lee Sang-in,KRX ; Kim Byung-hee,KRX ; Lee Sang-min,KRX ; Park Chang-soo,KRX, Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature.
Alessandra Satta BE; Karen Maex BE; Kai-Erik Elers FI; Ville Antero Saanila FI; Pekka Juha Soininen FI; Suvi P. Haukka FI, Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
Gopinath,Sanjay; Dalton,Jeremie; Blackburn,Jason M.; Drewery,John; van den Hoek,Willibrordus Gerardus Maria, Method for enhancing the nucleation and morphology of ruthenium films on dielectric substrates using amine containing compounds.
Andricacos Panayotis Constantinou ; Cabral ; Jr. Cyril ; Parks Christopher Carr ; Rodbell Kenneth Parker ; Tsai Roger Yen-Luen, Method for forming electromigration-resistant structures by doping.
Rhodes Howard E. (Boise ID) Fazan Pierre C. (Boise ID) Chan Hiang C. (Boise ID) Dennison Charles H. (Boise ID) Liu Yauh-Ching (Boise ID), Method for forming low resistance DRAM digit-line.
Yu Chang (Boise ID) Doan Trung T. (Boise ID) Sandhu Gurtej S. (Boise ID), Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point meta.
Greer,Harold F. R.; Fair,James A.; Sung,Junghwan; Draeger,Nerissa Sue, Method for preventing and cleaning ruthenium-containing deposits in a CVD apparatus.
Wei Che C. (Plano TX) Zaccherini Chiara (Milan TX ITX) Miller Robert O. (The Colony TX) Dixit Girish A. (Dallas TX), Method for self-aligned polysilicon contact formation.
Sandhu Gurtej S. (Boise ID) Doan Trung T. (Boise ID) Yu Chang (Boise ID), Method for simultaneously forming silicide and effecting dopant activation on a semiconductor wafer.
Bocko Peter L. (Painted Post NY) Wein William J. (Corning NY) Young Charles E. (Watkins Glen NY), Method for synthesizing MgO－Al2O3－SiO2glasses and ceramics.
Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.
Alessandro Cesare Callegari ; Fuad Elias Doany ; Evgeni Petrovich Gousev ; Theodore Harold Zabel, Methods for forming metal oxide layers with enhanced purity.
Granneman, Ernest H. A.; Kuznetsov, Vladimir; Pages, Xavier; van der Jeugd, Cornelius A., Methods of forming films in semiconductor devices with solid state reactants.
Boyd, John; Redeker, Fritz; Dordi, Yezdi; Yoon, Hyungsuk Alexander; Li, Shijian, Methods of post-contact back end of the line through-hole via integration.
Jer-shen Maa ; Yoshi Ono ; Fengyan Zhang, Nickel silicide including iridium for use in ultra-shallow junctions with high thermal stability and method of manufacturing the same.
Gardiner Robin A. ; Kirlin Peter S. ; Baum Thomas H. ; Gordon Douglas ; Glassman Timothy E. ; Pombrik Sofia ; Vaartstra Brian A., Precursor compositions for chemical vapor deposition, and ligand exchange resistant metal-organic precursor solutions.
Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
Allardyce George R. (Nuneaton GBX) Davies Anthony J. (Nuneaton GBX) Wayness David J. (Brownsover GBX) Singh Amrik (Hillfields GBX), Process for multilayer printed circuit board manufacture.
Wuu Shou-Gwo (Chu-Gong Hsinchu TWX) Liang Mong-Song (Hsin-chu TWX) Wang Chuan-Jung (Chu-Tong TWX) Su Chung-Hui (Hsinchu TWX), Process of making a polysilicon barrier layer in a self-aligned contact module.
Stephen N. Vaughn ; Peter G. Ham ; Keith H. Kuechler, Process to control conversion of C4+ and heavier stream to lighter products in oxygenate conversion reactions.
Kai-Erik Elers FI; Ville Antero Saanila FI; Sari Johanna Kaipio FI; Pekka Juha Soininen FI, Production of elemental thin films using a boron-containing reducing agent.
Rautenstrauch Valentin,CHX ; Vanhessche Koenraad P. M. ; Genet Jean-Pierre,FRX ; Lenoir Jean-Yves,FRX, Ruthenium catalysts and their use in the asymmetric hydrogenation of cyclopentenones.
Matsuo Mie,JPX ; Okano Haruo,JPX ; Hayasaka Nobuo,JPX ; Suguro Kyoichi,JPX ; Miyajima Hideshi,JPX ; Wada Jun-ichi,JPX, Semiconductor device having a metal film formed in a groove in an insulating film.
Masayuki Shimizu JP, Semiconductor device having fluorined insulating film and reduced fluorine at interconnection interfaces and method of manufacturing the same.
Marsh, Eugene P.; Uhlenbrock, Stefan, Solvated ruthenium precursors for direct liquid injection of ruthenium and ruthenium oxide and method of using same.
Nguyen Tue ; Charneski Lawrence J. ; Evans David R. ; Hsu Sheng Teng, System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides.
Price J. B. (Scottsdale AZ) Tobin Philip J. (Scottsdale AZ) Pintchovski Fabio (Mesa AZ) Seelbach Christian A. (San Jose CA), Titanium nitride MOS device gate electrode and method of producing.
Metz,Matthew V.; Datta,Suman; Doczy,Mark L.; Kavalieros,Jack T.; Brask,Justin K.; Chau,Robert S., Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors.
Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.