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A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without o

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

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1. A system for a multiple chip architecture comprising: a first system on-chip (SoC), located on a substrate, comprising a first core, one or more first peripheral components, and a first on-chip bus system with a first system address map, wherein the first on-chip bus system is configured to enabl

1. A system for a multiple chip architecture comprising: a first system on-chip (SoC), located on a substrate, comprising a first core, one or more first peripheral components, and a first on-chip bus system with a first system address map, wherein the first on-chip bus system is configured to enable access with a first on-chip bus protocol between the first core and the one or more first peripheral components based on the first system address map; a second SoC comprising a second core, one or more second on-chip peripheral components and a second on-chip bus system with a second system address map, wherein the second on-chip bus system is configured to enable access with a second on-chip bus protocol between the second core and the one or more second peripheral components; and a transparent interface configured to enable communication between the first on-chip bus system of the first SoC and the second on-chip bus system of the second SoC in response to being communicatively coupled to one another based on a consistent system address map comprising a plurality of addresses that include unique and non-overlapping addresses from one another,wherein the first on-chip bus protocol and the second on-chip bus protocol are the same bus protocol. 2. The system of claim 1, wherein the first core comprises a first computer processing unit (CPU) configured to operate at a first frequency via the first on-chip bus protocol and the second core comprises a second CPU configured to operate at a second frequency that is different than the first frequency via the second on-chip bus protocol. 3. The system of claim 1, wherein the first on-chip bus protocol of the first on-chip bus system and the second on-chip bus protocol of the second on-chip bus system are configured to operate in a synchronous mode with respect to one another, and wherein the transparent interface is synchronized to both on-chip bus frequencies of the first on-chip bus system and the second on-chip bus system. 4. The system of claim 1, wherein the first on-chip bus protocol of the first on-chip bus system and the second on-chip bus protocol of the second on-chip bus system are configured to operate in an asynchronous mode with respect to one another, and wherein the transparent interface is synchronized to only one of the first on-chip bus system or the second on-chip bus system. 5. The system of claim 1, wherein the first on-chip bus system comprises a phase locked loop configured to generate a clock that corresponds to operations of the first on-chip bus system and the second on-chip bus system. 6. The system of claim 1, wherein the first SoC is configured according to a non-volatile memory compatible based technology with a first feature size that is different from a second feature size of the second SoC configured according to a non-volatile memory incompatible based technology, wherein the first feature size enables compatibility for the communication with a Flash memory of the one or more first peripheral components, wherein the transparent interface is further configured to enable communication between the second on-chip bus system and the Flash memory. 7. The system of claim 1, further comprising: a fallback component configured to, in response to a detection of a failure of the first SoC or the second SoC, enable an other of the first or the second SoC to operate a sub-system via the transparent interface. 8. The system of claim 1, wherein the first on-chip bus system comprises a first arbitration component configured to control arbitration of access requests from a plurality of master agents of the first SoC, while a second arbitration component of the second on-chip bus system is at least partially disabled, and combine access grants from the second arbitration component and the plurality of master agents of the first SoC. 9. The system of claim 1, wherein the transparent interface is further configured to provide a protection component between the first on-chip bus protocol and the second on-chip bus protocol by enabling error correction code/error detection code of the first SoC and the second SoC to transparently extend coverage of the consistent system address map with the unique and non-overlapping addresses between the first SoC and the second SoC. 10. The system of claim 1, wherein the first on-chip bus system comprises a first interrupt component configured to arbitrate among interrupts mapped to the second SoC, and route winning interrupt signals to a second interrupt component of the second on-chip bus system via the transparent interface. 11. The system of claim 1, wherein the first on-chip bus system and the second on-chip bus system comprise one or more access protection components configured to assign one or more unique tag identifiers (IDs) to one or more master agents, wherein the one or more unique tag IDs enable slave agents to identify the corresponding master agents and further enable transparent access via the transparent interface to the one or more first on-chip peripheral components or the one or more second on-chip peripheral components based on the one or more unique tag IDs. 12. A method for a system comprising: communicating, using a first on-chip bus protocol via a first on-chip bus on a first system on-chip (SoC), between a first core and one or more of a plurality of first peripheral components, located on a same substrate, based on a first system address map with first addresses corresponding to the plurality of first peripheral components and the first core;communicating, using a second on-chip bus protocol via a second on-chip bus on a second SoC, between a second core and one or more of a plurality of second peripheral components of the second SoC based on a second system address map with addresses corresponding to the plurality of second peripheral components and the second core; andenabling communication, via a transparent interface, between the first SoC and the second SoC based on a system address map comprising unique and non-overlapping addresses of the first system address map and the second system address map,wherein the first on-chip bus protocol and the second on-chip bus protocol are the same bus protocol. 13. The method of claim 12, further comprising: arbitrating, via the transparent interface, access requests from master agents of the first SoC and the second SoC to the unique and non-overlapping addresses of the system address map corresponding to the plurality of first peripheral components or the plurality of second peripheral components. 14. The method of claim 13, wherein the arbitrating the access requests further comprises: synchronizing, via a handshake protocol, arbitration between a first arbitration component of the first on-chip bus and a second arbitration component of the second on-chip bus;arbitrating access requests from the master agents of the first SoC via the first arbitration component of the first on-chip bus and disabling a second arbitration component of the second on-chip bus in response to the handshake protocol; and combining access grants from the master agents of the first SoC and the second SoC. 15. The method of claim 12, further comprising: extending an error correction code protection/error detection code protection via the transparent interface to include both a first on-chip bus protocol utilized by the first on-chip bus and a second on-chip bus protocol by the second on-chip bus. 16. The method of claim 11, further comprising: operating the first core with one or more first computer processing units and the second core with one or more second computer processing units having different operating frequencies than the first computer processing units. 17. The method of claim 11, further comprising: enabling, via the transparent interface, communication with a non-volatile memory of the plurality of first peripheral components at the first SoC from the second SoC comprising a smaller feature size than the first SoC that makes the second on-chip bus incompatible with any non-volatile memory on the second SoC. 18. An apparatus for a multiple chip architecture comprising: a first system on-chip (SoC), comprising a first core and one or more first peripheral components on a substrate, configured to enable communication among the first core and the one or more first peripheral components via a first on-chip bus protocol of a first on-chip bus based on a first system map with a first plurality of addresses corresponding to the first core and the one or more first peripheral components; anda transparent interface configured to enable communication between the first on-chip bus and a second on-chip bus of a second SoC when coupled to one another based on a consistent system address map comprising unique and non-overlapping addresses corresponding to the first core, the one or more peripheral components, a second core of the second SoC and one or more second peripheral components of the second SoC, wherein the second core and the one or more second peripheral components are configured to communicate among one another via a second on-chip bus based on a second system map,wherein the first on-chip bus protocol and the second on-chip bus protocol are the same bus protocol. 19. The apparatus of claim 18, wherein the first on-chip bus system comprises a first arbitration component configured to control arbitration of access requests from a plurality of master agents of the first SoC while a second arbitration component of the second on-chip bus system is at least partially disabled, and combine access grants from the second arbitration component and the plurality of master agents of the first SoC to determine winning grants for access to a slave agent. 20. The apparatus of claim 18, wherein the first SoC and the second SoC are coupled together on a same substrate, and one of the first SoC or the second SoC comprises a physical connection pad while an other one of the first SoC or the second SoC is without any physical connection pad and configured to communicate with external components via the physical connection pad. 21. The apparatus of claim 18, wherein the transparent interface utilizes a single phase locked loop located at one of the first SoC or the second SoC to control a synchronization of communications of between the first SoC and the second SoC. 22. The apparatus of claim 18, wherein the transparent interface is configured to enable communication between the second on-chip bus system and a Flash memory of the one or more first peripheral components of the first SoC, wherein the first SoC, wherein the first SoC is configured according to a non-volatile memory compatible based technology with a larger feature size than a smaller feature size of the second SoC configured according to a non-volatile memory incompatible based technology, wherein the larger feature size enables the communication with a Flash memory of the one or more first peripheral components. 23. The apparatus of claim 18, wherein the first on-chip bus system and the second on-chip bus system comprise one or more access protection components configured to assign one or more unique tag identifiers (IDs) to one or more master, wherein the one or more unique tag IDs enable slave agents to identify the corresponding master agents and further enable transparent access via the transparent interface to the one or more first on-chip peripheral components or the one or more second on-chip peripheral components based on the one or more unique tag IDs. 24. The apparatus of claim 18, wherein the first on-chip bus system comprises a first interrupt component configured to arbitrate among interrupts mapped to the second SoC, and route winning interrupt signals to a second interrupt component of the second on-chip bus system via the transparent interface. 25. The apparatus of claim 24, wherein the first SoC is further configured to signal one or more interrupt triggers to an interrupt service provider on the second SoC via one or more dedicated interrupt trigger connections.