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According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. T

According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.

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1. A semiconductor device comprising: a first voltage generator circuit which outputs a first voltage to a first node;a second voltage generator circuit which outputs a second voltage to a second node;a third voltage generator circuit which outputs a third voltage to a third node;a first MOS transis

1. A semiconductor device comprising: a first voltage generator circuit which outputs a first voltage to a first node;a second voltage generator circuit which outputs a second voltage to a second node;a third voltage generator circuit which outputs a third voltage to a third node;a first MOS transistor capable of short-circuiting the first node and the second node;a second MOS transistor capable of short-circuiting the second node and the third node; anda controller which performs a control operation to short-circuit the first node and the second node by turning on the first MOS transistor, controlling a length of a period in which the first MOS transistor is kept in an onON state based on time,wherein the controller simultaneously performs on and off switching operations of the first MOS transistor and second MOS transistor. 2. The device according to claim 1, wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node, andwhenif a potential of the first load reaches the second voltage in a case whereand the first voltage is higher than the second voltage atduring a read timeoperation, the controller turns off the first MOS transistor. 3. The device according to claim 1, wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node, andin a case whereif the second voltage is higher than the first voltage atduring a read timeoperation, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage. 4. The device according to claim 1, wherein the first MOS transistor is one of an n-type intrinsic MOS transistor, a depression-type MOS transistor, and an enhancement-type MOS transistor. 5. The device according to claim 1, wherein the controller senses a potential of the second node, andtransfersoutputs a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor. 6. The device according to claim 1, further comprising: a third voltage generator circuit which outputs a third voltage to a third node; anda second MOS transistor capable of short-circuiting the second node and the third node,wherein the controller simultaneously performs on and off switching operations of the first MOS transistor and second MOS transistor. 7. The device according to claim 61, wherein the controller senses a potential of one of the second node and the third node, and transfersoutputs to the gates of the first and second MOS transistors one of (a) a first voltage equal to the sum of the above potential and a first threshold voltage of the first MOS transistor, and(b) a second voltage equal to the sum of the above potential and a second threshold voltage of the second MOS transistor to the gates of the first and second MOS transistors. 8. The device according to claim 1, further comprising: a memory cell array including plural memory cells whose current paths are serially connected and, each of which includesthe memory cells including a charge storage layer and control gate; andword lines connected to the control gates of the memory cells and, each of the word lines being used as one of the first and second loads;wherein the first and second voltage generator circuits transfer one of the first and second voltages to the word lines. 9. A semiconductor device comprising: a memory cell array including i memory cells (wherein i is an integral number larger than 2) capable of holding data each of which includes a charge storage layer and control gate and the i memory cells are serially connected along a current path; anda voltage generator circuit which generates a first voltage and a second voltage, transferring the first and the second voltages to word lines connected to the control gates of the memory cells,wherein the voltage generator circuittransfersoutputs the first voltage to the word line connected to the control gate of a jth one of the ith memory cellcells, andtransfersoutputs the second voltage to the word lines connected to the control gates of the (i+1)th and (i+2)th(j+1) and (j+2)th memory cells which are arranged on a drain side of the ithjth memory cell. 10. The device according to claim 9, wherein the first voltage is a voltage corresponding to data held by the ithjth memory cell. 11. The device according to claim 9, further comprising: a MOS transistor capable of short-circuiting a first node and a second node; anda controller which performs a control operation to turn on the MOS transistor to short-circuit the first node and the second node, whereinthe voltage generator circuit includes a first voltage generator circuit which generates the first voltage and outputs the first voltage to the first node, anda second voltage generator circuit which generates the second voltage and outputs the second voltage to the second node, andthe controller controls a length of a period in which the MOS transistor is maintained in an onON state based on time. 12. The device according to claim 11, wherein the controller senses a potential of the second node, andtransfersoutputs a voltage equal to the sum of the above potential and a threshold voltage of the MOS transistor to the gate of the MOS transistor. 13. The device according to claim 9, wherein the MOS transistor is one of an n-type intrinsic MOS transistor, a depression-type MOS transistor, and an enhancement-type MOS transistor. 14. The device according to claim 11, wherein a word line used as a first load is connected to the first node, and a word line used as a second load larger than the first load is connected to the second node, and in a case whereif the second voltage is higher than the first voltage, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage. 15. A control method of a semiconductor device comprising: causing a first voltage generator circuit to generate a first voltage and output the first voltage to a first node;causing a second voltage generator circuit to generate a second voltage and output the second voltage to a second node;causing a third voltage generator circuit to generate a third voltage and output the third voltage to a third node;causing a controller to set a first MOS transistor in an onON state and short-circuit the first node and the second node;causing a controller to set a second MOS transistor in an ON state and short-circuit the second node and third node;causing the controller to turn on the first and second MOS transistors and short-circuit the first, second and third nodes;causing the controller to simultaneously perform on and off switching operations of the first and second MOS transistors; andcausing the controller to control a length of a period in which the first MOS transistor is maintained in the onON state based on time. 16. The method according to claim 15, further comprising: causing the first voltage generator circuit to transferoutput the first voltage to a first load via the first node;causing the second voltage generator circuit to transferoutput the second voltage higher than the first voltage to a second load larger than the first load via the second node; andcausing the controller to turn off the first MOS transistor before a potential of the second load reaches the first voltage. 17. The method according to claim 15, further comprising: causing the first voltage generator circuit to transferoutput the first voltage to a first load via the first node;causing the second voltage generator circuit to transferoutput the second voltage to a second load larger than the first load via the second node; andif the first voltage is higher than the second voltage atduring a read timeoperation, causing the controller to turn off the first MOS transistor at the timing ofwhen a potential of the first load reachingreaches the second voltage. 18. The method according to claim 15, further comprising: causing the controller to sense a potential of the second node; andcausing the controller to transferoutput a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor. 19. The method according to claim 15, further comprising: causing a third voltage generator circuit to generate a third voltage and output the third voltage to a third node;causing the controller to turn on the first and second MOS transistors and short-circuit the first to third nodes; andcausing the controller to simultaneously perform on and off switching operations of the first and second MOS transistors. 20. The method according to claim 16, further comprising: transferringoutputting the first voltage to a control gate of an ith memory cell among plural memory cells whose current paths are serially connected via the first node atduring a data read timeoperation; andtransferring the second voltage to a control gate of an (i+1)th memory cell arranged on a drain side of the ith memory cell via the second node. 21. A semiconductor device comprising: a first voltage generator including a first charge pump, the first voltage generator being configured capable of outputting a first read voltage to a first node;a second voltage generator including a second charge pump, the second voltage generator being configured capable of outputting a second read voltage different from the first read voltage to a second node;a third voltage generator including a third charge pump, the third voltage generator being configured capable of outputting a third read voltage different from each of the first and second read voltages to a third node;a first MOS transistor configured capable of short-circuiting the first node and the second node;a second MOS transistor configured capable of short-circuiting the second node and the third node; anda first controller configured capable of performing a control operation, the first controller being configured to turn on the first MOS transistor and the second MOS transistor in the control operation,wherein the first, second and third read voltages are each a voltage sufficient to turn on a memory transistor. 22. The semiconductor device according to claim 21, wherein the first voltage generator includes a first charge pump controller and the second voltage generator includes a second charge pump controller. 23. The semiconductor device according to claim 21, wherein the first MOS transistor is a MOS transistor with a high withstand voltage. 24. The semiconductor device according to claim 21, wherein the first controller is configured capable of short-circuiting the second node and third node by turning on the second MOS transistor in the control operation. 25. The semiconductor device according to claim 21, wherein an input node of the first charge pump is electrically connected to an output node of the first charge pump controller and an input node of the first charge pump controller is electrically connected to an output node of the first charge pump. 26. The semiconductor device according to claim 25, wherein an input node of the second charge pump is electrically connected to an output node of the second charge pump controller and an input node of the second charge pump controller is electrically connected to an output node of the second charge pump. 27. The semiconductor device according to claim 21, wherein an input node of the third charge pump is electrically connected to an output node of the third charge pump controller and an input node of the third charge pump controller is electrically connected to an output node of the third charge pump. 28. A semiconductor device comprising: a first voltage generator including a first charge pump, the first voltage generator being configured to output a first voltage to a first node;a second voltage generator including a second charge pump, the second voltage generator being configured to output a second voltage to a second node;a third voltage generator including a third charge pump, the third voltage generator being configured to output a third voltage to a third node;a first MOS transistor configured to short-circuit the first node and the second node;a second MOS transistor configured to short-circuit the second node and the third node; anda first controller configured capable of performing a control operation, the first controller being configured to short-circuit the first node and second node at by turning on the first MOS transistor in the control operation. 29. The semiconductor device according to claim 28, further comprising: the first controller being configured to short-circuit the second node and third node by turning on the second MOS transistor. 30. The semiconductor device according to claim 28, wherein the first voltage generator includes a first charge pump controller, the second voltage generator includes a second charge pump controller and the third voltage generator includes a third charge pump controller. 31. The semiconductor device according to claim 28, wherein the first MOS transistor is a MOS transistor with a high withstand voltage. 32. The semiconductor device according to claim 29, wherein the first controller is configured to short-circuit the first node, second node and third node by turning on the first and second MOS transistors in the control operation. 33. The semiconductor device according to claim 29, wherein an input node of the first charge pump is electrically connected to an output node of the first charge pump controller and an input node of the first charge pump controller is electrically connected to an output node of the first charge pump. 34. A semiconductor device comprising: a first voltage generator including a first charge pump, the first voltage generator being configured capable of outputting a first voltage to a first node;a second voltage generator including a second charge pump, the second voltage generator being configured capable of outputting a second voltage to a second node;a third voltage generator including a third charge pump, the third voltage generator being configured capable of outputting a third voltage to a third node;a first MOS transistor configured capable of short-circuiting the first node and the second node;a second MOS transistor configured capable of short-circuiting the second node and the third node; andmeans for performing a control operation to short-circuit the first node and the second node by turning on the first MOS transistor. 35. The semiconductor device according to claim 34, wherein the means for performing is configured to short-circuit the first node to the second node during rising voltage of either the first node or the second node. 36. The semiconductor device according to claim 34, wherein at least one of the first voltage and the second voltage are rising when the first node is connected to the second node. 37. The semiconductor device according to claim 34, wherein the first voltage generator includes a first charge pump controller and the second voltage generator includes a second charge pump controller. 38. The semiconductor device according to claim 34, wherein the first MOS transistor is a MOS transistor with a high withstand voltage. 39. The semiconductor device according to claim 34, wherein the means for performing is also configured to turn on the second MOS transistor so that the second node is short-circuited to the third node. 40. The semiconductor device according to claim 39, wherein the means for performing is configured to short-circuit the second node to the third node during rising voltage of at least one of the first node, the second node, and the third node. 41. The semiconductor device according to claim 39, wherein at least one of the first voltage, the second voltage, and the third voltage is rising when the second node is connected to the third node. 42. A semiconductor device comprising: a first voltage generator including a first charge pump, the first voltage generator being configured capable of outputting a first voltage to a first node;a second voltage generator including a second charge pump, the second voltage generator being configured capable of outputting a second voltage to a second node;a third voltage generator including a third charge pump, the third voltage generator being configured capable of outputting a third voltage to a third node;a first MOS transistor disposed between the first and second nodes;a second MOS transistor disposed between the first and second nodes;means for performing a first control operation to short-circuit the first node and the second node by turning on the first MOS transistor; andmeans for performing a second control operation to short-circuit the second node and the third node by turning on the second MOS transistor.