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Memory array with flash and random access memory and method therefor, reading data from the flash memory without storing the data in the random access memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
  • G11C-011/00
  • G11C-016/10
  • G06F-013/42
  • G06F-003/06
  • G06F-013/38
  • G06F-012/02
  • G06F-012/0868
  • G06F-012/06
출원번호 US-0663099 (2012-10-29)
등록번호 US-10096350 (2018-10-09)
발명자 / 주소
  • Walsh, Kevin K.
  • Gordon, Charles R.
  • Solheim, Paul R.
  • Reiland, Jerry D.
  • Musto, Robert D.
  • Bigelow, Duane R.
출원인 / 주소
  • Medtronic, Inc.
인용정보 피인용 횟수 : 0  인용 특허 : 25

초록

Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory arr

대표청구항

1. A memory array for storing data, comprising: a flash memory array;a random access memory array operatively coupled to said flash memory, said random access memory and said flash memory configured to receive said data;a memory management module operatively coupled to said random access memory arra

이 특허에 인용된 특허 (25)

  1. Ghercioiu, Marius; Hedesiu, Horea; Folea, Silviu; Crisan, Gratian I.; Ceteras, Ciprian; Monoses, Ioan, Deployment and execution of a graphical program on an embedded device from a PDA.
  2. Okyay, Aysel Yildiz; Nguyen, Luu Ngoc; Richmond, Gregory Jon, Download sequencing techniques for circuit configuration data.
  3. Mann, Alfred E.; Causey, III, James D.; Haubach, Alan; Malave, Luis J.; Livingston, John; Hague, Cliff; Srisathapat, Chad; Yonemoto, Jay; Ruppert, Deborah; Bishop, Dennis P.; Gut, Adrian; Murtfeldt, , External infusion device with remote programming bolus estimator and/or vibration alarm capabilities.
  4. Roy, Richard S.; Sikdar, Dipak Kumar, Hierarchical multi-bank multi-port memory organization.
  5. McElroy David J. (Houston TX), High density floating gate electrically programmable ROM.
  6. Richard D. Pashley ; Mark D. Winston ; Owen W. Jungroth ; David J. Kaplan, Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array.
  7. Coulthard,John J., Load safeguard systems.
  8. Johnson Mark J. (Algonquin IL) Branson Brian D. (Austin TX), Memory having nonvolatile and volatile memory banks.
  9. Klint,Jani, Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit.
  10. Barber, Douglas; Meyer, Kevin, Method and apparatus for low power operation of an RF wireless modem.
  11. Moberg, Sheldon B.; Hanson, Ian B.; Talbot, Cary D.; Ireland, Jeffrey, Methods and apparatuses for detecting medical device acceleration, temperature, and humidity conditions.
  12. Luk, Shun Hang; Bruce, Rey H.; Bruce, Ricardo H.; Bultman, Dave L., Network storage device having solid-state non-volatile memory.
  13. Prabhakar, Venkatraman, Non-volatile latch with low voltage operation.
  14. Adams, Lewis, Optimum power management of system on chip based on tiered states of operation.
  15. Walsh Kevin K. ; Thompson David L., Peripheral memory patch and access method for use with an implantable medical device.
  16. Ledzius, Robert C.; Flemmons, James L.; Maturo, Lawrence R., Reconfigurable computing system and method and apparatus employing same.
  17. Cohen, Itzic; Tirosh, Ori; Danon, Kobi; Hadas, Shmulik, Recovery while programming non-volatile memory (NVM).
  18. Zampaglione, Michael Anthony; Tooher, Michael, SRAM leakage reduction circuit.
  19. Kaki Kenichi,JPX ; Katayama Kunihiro,JPX ; Tsunehiro Takashi,JPX, Semiconductor disk storage apparatus including a write buffer memory in which instructions are sequentially fed to a plurality of flash memories to continuously write sectors of data in an overlapped.
  20. Matsuo Ryuichi (Hyogo JPX) Wada Tomohisa (Hyogo JPX) Hirayama Kazutoshi (Hyogo JPX) Ohbayashi Shigeki (Hyogo JPX), Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of ope.
  21. Kaki Kenichi (Yokohama JPX) Katayama Kunihiro (Yokohama JPX) Tsunehiro Takashi (Ebina JPX), Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality o.
  22. Sabharwal, Deepak; Shubat, Alexander, Source-biased SRAM cell with reduced memory cell leakage.
  23. Yamagami, Hajime; Terada, Kouichi; Hayashi, Yoshihiro; Tsunehiro, Takashi; Katayama, Kunihiro; Kaki, Kenichi; Furuno, Takeshi, Storage device employing a flash memory.
  24. Li, Shaojie; Nguyen, Truc, System and method to support out-band storage subsystem management via SCSI bus when operating power to a computer system is off.
  25. Russell R. Roeber ; James M. Gray, Thermal recorder for use with battery-powered equipment.
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