초록

A method to integrate a vertical IMPATT diode in a planar process.

대표청구항 ▼

1. An IMPATT diode, comprising: a substrate;a p-type region and an n-type region that are vertically arranged on the substrate, the n-type region including a lightly doped n-type layer and a heavily doped n-type layer, the p-type region and the lightly doped n-type layer being in contact with each o

1. An IMPATT diode, comprising: a substrate;a p-type region and an n-type region that are vertically arranged on the substrate, the n-type region including a lightly doped n-type layer and a heavily doped n-type layer, the p-type region and the lightly doped n-type layer being in contact with each other and forming an IMPATT diode junction;a vertical access to the highly doped n-type region;an isolation structure disposed between and configured to isolate the vertical access and the p-type region; andtwo Ohmic contacts, on a top surface of the IMPATT diode, electrically coupled to the vertical access and the p-type region from the top surface of the IMPATT diode. 2. The diode of claim 1, further comprising: an un-doped layer extending below the isolation structure, the un-doped layer interposed between the vertical access and the light doped n-type layer. 3. The diode of claim 1, further comprising: a deep trench isolation structure laterally surrounding the n-type region and extending to the substrate. 4. The diode of claim 1, further comprising: a buried oxide layer interposed between the n-type region and the substrate. 5. The diode of claim 1, wherein the p-type region includes a p-doped SiGe layer interfacing with the n-type region. 6. The diode of claim 1, wherein the n-type region includes an n-doped SiGe layer interfacing the bottom surface of the p-type region. 7. The diode of claim 1, wherein the n-type region includes a vertical portion interfacing with the bottom surface of the p-type region, the vertical portion having a lower doping concentration than the p-type region. 8. The diode of claim 1, wherein the n-type region includes: a first vertical portion laterally surrounding the isolation structure;a buried layer positioned on the substrate and under the p-type region, the buried layer contacting the first vertical portion; anda second vertical portion laterally surrounded by the isolation structure and the first vertical portion, the second vertical portion vertically interposed between the buried layer and the p-type region, the second vertical portion interfacing with the bottom surface of the p-type region. 9. The diode of claim 8, wherein the second vertical portion is separated from the first vertical portion. 10. The diode of claim 8, wherein the second vertical portion contacts the first vertical portion. 11. A method of making an IMPATT diode, comprising: providing a substrate;providing a p-type region and an n-type region that are vertically arranged on the substrate, the n-type region including a lightly doped n-type layer and a heavily doped n-type layer, the p-type region and the lightly doped n-type layer being in contact with each other and forming an IMPATT diode junction;providing a vertical access to the highly doped n-type region;providing an isolation structure disposed between and configured to isolate the vertical access and the p-type region; andproviding two Ohmic contacts, on a top surface of the IMPATT diode, electrically coupled to the vertical access and the p-type region from the top surface of the IMPATT diode. 12. The method of claim 11, further comprising providing an un-doped layer extending below the isolation structure, the un-doped layer interposed between the vertical access and the light doped n-type layer. 13. The method of claim 11, further comprising providing a deep trench isolation structure laterally surrounding the n-type region and extending to the substrate. 14. The method of claim 11, further comprising a buried oxide layer interposed between the n-type region and the substrate. 15. The method of claim 11, wherein the p-type region includes a p-doped SiGe layer interfacing with the n-type region. 16. The method of claim 11, wherein the n-type region includes an n-doped SiGe layer interfacing the bottom surface of the p-type region. 17. The method of claim 11, wherein the n-type region includes a vertical portion interfacing with the bottom surface of the p-type region, the vertical portion having a lower doping concentration than the p-type region. 18. The method of claim 11, wherein the n-type region includes: a first vertical portion laterally surrounding the isolation structure;a buried layer positioned on the substrate and under the p-type region, the buried layer contacting the first vertical portion; anda second vertical portion laterally surrounded by the isolation structure and the first vertical portion, the second vertical portion vertically interposed between the buried layer and the p-type region, the second vertical portion interfacing with the bottom surface of the p-type region. 19. The method of claim 18, wherein the second vertical portion is separated from the first vertical portion.