Band-gap reference circuit with chopping circuit
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/10
G05F-003/02
G05F-003/26
H03K-017/687
H03F-003/38
출원번호
US-0282339
(2016-09-30)
등록번호
US-10114400
(2018-10-30)
발명자
/ 주소
Lacy, Cameron
Lynch, Michael W.
Uhanov, Sergei
출원인 / 주소
Synopsys, Inc.
대리인 / 주소
Bever, Hoffman & Harms, LLP
인용정보
피인용 횟수 :
0인용 특허 :
2
초록▼
A BGR circuit for sub-1V ICs utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a CTAT stage, a PTAT stage, and an output stage. The voltage chopping circ
A BGR circuit for sub-1V ICs utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a CTAT stage, a PTAT stage, and an output stage. The voltage chopping circuit reduces input offset and 1/f noise by periodically alternating (time-averaging) the negative temperature dependent and positive temperature dependent voltages supplied by the CTAT and PTAT stages to the op-amp's input terminals. The current chopping circuit minimizes current variations caused by process-related differences in the current mirror devices by periodically alternating (time-averaging) three balanced currents generated by the current mirror circuit such that each current is transmitted equally to each of the CTAT, PTAT and output stages. The filter serves to maintain loop stability and remove the low frequency noise generated by the applied voltage and/or current chopping operations.
대표청구항▼
1. A bandgap reference (BGR) circuit for generating a reference voltage, the BGR circuit comprising: an operational amplifier (op-amp) having a first op-amp input terminal and a second op-amp input terminal;a current mirror circuit including first, second and third transistors having first terminals
1. A bandgap reference (BGR) circuit for generating a reference voltage, the BGR circuit comprising: an operational amplifier (op-amp) having a first op-amp input terminal and a second op-amp input terminal;a current mirror circuit including first, second and third transistors having first terminals connected to a voltage source and having gate terminals coupled by way of a gate control line to at least one output node of the op-amp such that the first, second and third transistors are controlled to respectively pass first, second and third currents to first, second and third signal lines in response to an op-amp output signal generated by said op-amp and transmitted on said gate control line;a first stage coupled to said current mirror circuit and configured to generate a negative temperature dependent voltage in response to at least one of said first, second and third currents, said negative temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a second stage coupled to said current mirror circuit and configured to generate a positive temperature dependent voltage in response to at least one of one of said first, second and third currents, said positive temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a third stage coupled to said current mirror circuit and configured to generate said reference voltage in accordance with at least one of the first, second and third currents;a voltage chopping circuit coupled to said op-amp, said voltage chopping circuit configured to periodically alternately apply said negative temperature dependent voltage and said positive temperature dependent voltage to said first and second op-amp input terminals, anda current chopping circuit connected to said first, second and third signal lines and configured to periodically alternately apply each of said first, second and third currents to said first, second and third stages such that transmission of each of said first, second and third currents is time-averaged between said first, second and third stages; anda filter configured to filter out noise generated by operation of said at least one of the voltage chopping circuit and the current chopping circuit,wherein said current chopping circuit comprises:a three-phase clock generator configured to generate a second clock signal, a third clock signal, and a fourth clock signal such that only said second clock signal is asserted during a first phase of a three-phase cycle, such that only said third clock signal is asserted during a second phase of the three phase cycle, and such that only said fourth clock signal is asserted during a third phase of the three phase cycle, anda three-phase switching circuit connected between said first, second and third signal lines and said first, second and third stages and configured such that said first, second and third signal lines are respectively coupled to said first, third and second stages during said first phase of said three-phase cycle, such that said first, second and third signal lines are respectively coupled to said second, first and third stages during said second phase of said three-phase cycle, and such that said first, second and third signal lines are respectively coupled to said third, first and second stages during said third phase of said three-phase cycle, wherein said three-phase clock generator is configured to generate said second, third, and fourth clock signals as a function of said first clock signal such that said second clock signal is asserted during an entire first phase of said first clock signal, said third clock signal is asserted during an entire subsequent second phase of said first clock signal, and said fourth clock signal is asserted during an entire subsequent third phase of said first clock signal. 2. The BGR circuit of claim 1, wherein said voltage chopping circuit comprising: an input voltage chopper coupled between said first and second op-amp input terminals and said first and second stages, said input voltage chopper configured such that said negative temperature dependent voltage and said positive temperature dependent voltage are respectively applied to said first and second op-amp input terminals during each first phase of a first clock signal, whereby the op-amp generates a first output signal during said each first phase, and such that said negative temperature dependent voltage and said positive temperature dependent voltage are respectively applied to said second and said first op-amp input terminals during each second phase of said first clock signal, whereby the op-amp generates a second output signal during said each second phase; andan output voltage chopper coupled between said op-amp and the gate control line, said output voltage chopper being configured to transmit said first output signal onto said gate control line during each said first phase, and to transmit said second output signal onto said gate control line during each said second phase. 3. The BGR circuit of claim 2, wherein said filter comprises an input filter connected between said gate control line and said voltage source, said input filter being configured to suppress low frequency noise generated by operation of said voltage chopping circuit. 4. The BGR circuit of claim 2, wherein said input voltage chopper comprises: a first switch configured to pass said negative temperature dependent voltage to said first op-amp input terminal during each said first phase of said first clock signal,a second switch configured to pass said positive temperature dependent voltage to said first op-amp input terminal during each said second phase of said first clock signal,a third switch configured to pass said negative temperature dependent voltage to said second op-amp input terminal during each said second phase of said first clock signal, anda fourth switch configured to pass said positive temperature dependent voltage to said second op-amp input terminal during each said first phase of said first clock signal. 5. The BGR circuit of claim 4, wherein the op-amp comprises a one-stage op-amp circuit including:first and second pull-down transistors respectively coupled between first and second output nodes and ground and having gate terminals that respectively form said first and second op-amp input terminals, andfirst and second pull-up transistors respectively coupled between a voltage source and said first and second output nodes;wherein the first and second switches are operably connected to the gate terminal of the first pull-down transistor and the third and fourth switches are operably connected to the gate terminal of the second pull-down transistor such that said first output signal is generated on said second output node during said each first phase of said first clock signal, and such that said second output signal is generated on said first output node during each said second phase of said first clock signal, andwherein said output voltage chopper includes:fifth and sixth switches configured to couple said second output node to said gate control line during each said first phase, and configured to couple said first output node to said gate control line during each said second phase, andseventh and eighth switches configured to couple gate terminals of the first and second pull-up transistors to said first output node during each said first phase, and configured to couple said gate terminals of the first and second pull-up transistors to said second output node during each said second phase. 6. The BGR circuit of claim 1, wherein said filter comprises: an input filter connected between said gate control line and said voltage source, said input filter being configured to suppress low frequency noise generated by operation of said voltage chopping circuit; andan output filter coupled to the output stage and configured to reduce noise generated by operation of said current chopping circuit. 7. The BGR circuit of claim 1, wherein said three-phase clock generator comprises a ring counter circuit. 8. The BGR circuit of claim 1, wherein said three-phase switching circuit comprises: a first switch group including a first plurality of switches configured to couple the first signal line to said first stage during each said first phase of said three-phase cycle, to couple the first signal line to said second stage during each said second phase of said three-phase cycle, and to couple the first signal line to said third stage during each said third phase of said three-phase cycle;a second switch group including a second plurality of switches configured to couple the second signal line to said third stage during each said first phase of said three-phase cycle, to couple the second signal line to said first stage during each said second phase of said three-phase cycle, and to couple the second signal line to said second stage during each said third phase of said three-phase cycle; anda third switch group including a third plurality of switches configured to couple the third signal line to said second stage during each said first phase of said three-phase cycle, to couple the third signal line to said third stage during each said second phase of said three-phase cycle, and to couple the third signal line to said first stage during each said third phase of said three-phase cycle. 9. A bandgap reference (BGR) circuit for generating a reference voltage, the BGR circuit comprising: an operational amplifier (op-amp) having a first op-amp input terminal and a second op-amp input terminal;a current mirror circuit including first, second and third transistors having first terminals connected to a voltage source and having gate terminals coupled by way of a gate control line to at least one output node of the op-amp such that the first, second and third transistors are controlled to respectively pass first, second and third currents to first, second and third signal lines in response to an op-amp output signal generated by said op-amp and transmitted on said gate control line;a first stage coupled to said current mirror circuit and configured to generate a negative temperature dependent voltage in response to at least one of said first, second and third currents, said negative temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a second stage coupled to said current mirror circuit and configured to generate a positive temperature dependent voltage in response to at least one of one of said first, second and third currents, said positive temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a third stage coupled to said current mirror circuit and configured to generate said reference voltage in accordance with at least one of the first, second and third currents;a voltage chopping circuit including:an input voltage chopper coupled between said op-amp and said first and second stages, said input voltage chopper configured to periodically alternately apply said negative temperature dependent voltage and said positive temperature dependent voltage to said first and second op-amp input terminals such that said negative temperature dependent voltage and said positive temperature dependent voltage are respectively applied to said first and second op-amp input terminals during a first time period, whereby the op-amp generates a first output signal during said first time period, and such that said negative temperature dependent voltage and said positive temperature dependent voltage are respectively applied to said second and said first op-amp input terminals during a second time period, whereby the op-amp generates a second output signal during said second time period; andan output voltage chopper coupled between said op-amp and the gate control line, said output voltage chopper being configured to transmit said first output signal onto said gate control line during said first phase, and to transmit said second output signal onto said gate control line during said second phase; anda current chopping circuit connected to said first, second and third signal lines and configured to periodically alternately apply each of said first, second and third currents to said first, second and third stages such that transmission of each of said first, second and third currents is time-averaged between said first, second and third stages,wherein said current chopping circuit comprises:a three-phase clock generator configured to generate a second clock signal, a third clock signal, and a fourth clock signal such that only said second clock signal is asserted during a first phase of a three-phase cycle, such that only said third clock signal is asserted during a second phase of the three phase cycle, and such that only said fourth clock signal is asserted during a third phase of the three phase cycle, anda three-phase switching circuit connected between said first, second and third signal lines and said first, second and third stages and configured such that said first, second and third signal lines are respectively coupled to said first, third and second stages during said first phase of said three-phase cycle, such that said first, second and third signal lines are respectively coupled to said second, first and third stages during said second phase of said three-phase cycle, and such that said first, second and third signal lines are respectively coupled to said third, first and second stages during said third phase of said three-phase cycle,wherein said three-phase clock generator is configured to generate said second, third, and fourth clock signals as a function of said first clock signal such that said second clock signal is asserted during an entire first phase of said first clock signal, said third clock signal is asserted during an entire subsequent second phase of said first clock signal, and said fourth clock signal is asserted during an entire subsequent third phase of said first clock signal. 10. The BGR circuit of claim 9, further comprising a filter connected between said gate control line and said voltage source, said filter being configured to suppress low frequency noise generated by operation of said voltage chopping circuit. 11. The BGR circuit of claim 9, wherein said input voltage chopper comprises: a first switch configured to pass said negative temperature dependent voltage to said first op-amp input terminal during said first time period,a second switch configured to pass said positive temperature dependent voltage to said first op-amp input terminal during said second time period,a third switch configured to pass said negative temperature dependent voltage to said second op-amp input terminal during said second time period, anda fourth switch configured to pass said positive temperature dependent voltage to said second op-amp input terminal during said first time period. 12. The BGR circuit of claim 11, wherein the op-amp comprises a one-stage op-amp circuit including first and second pull-down transistors respectively connected between first and second output nodes and ground and having gate terminals that respectively form said first and second op-amp input terminals, first and second pull-up transistors respectively coupled between a voltage source and said first and second output nodes such that said first output signal is generated on said second output node during said first time period, and such that said second output signal is generated on said first output node during said second time period, andwherein said output voltage chopper includes fifth and sixth switches configured to pass said first output signal to said gate control line during said first time period, and configured to pass said second output signal to said gate control line during said second time period. 13. The BGR circuit of claim 12, wherein the op-amp comprises a one-stage op-amp circuit including:first and second pull-down transistors respectively connected between first and second output nodes and ground and having gate terminals that respectively form said first and second op-amp input terminals, andfirst and second pull-up transistors respectively coupled between a voltage source and said first and second output nodes, andwherein the first and second switches are operably connected to the gate terminal of the first pull-down transistor and the third and fourth switches are operably connected to the gate terminal of the second pull-down transistor such that said first output signal is generated on said second output node during said first time period, and such that said second output signal is generated on said first output node during each said second time period. 14. The BGR circuit of claim 9, wherein said output voltage chopper comprises: fifth and sixth switches configured to couple said second output node to said gate control line during said first time period, and configured to couple said first output node to said gate control line during said second time period; andseventh and eighth switches configured to couple gate terminals of the first and second pull-up transistors to said first output node during said first time period, and configured to couple said gate terminals of the first and second pull-up transistors to said second output node during said second time period. 15. A bandgap reference (BGR) circuit for generating a reference voltage, the BGR circuit comprising: an operational amplifier (op-amp) having a first op-amp input terminal and a second op-amp input terminal;a current mirror circuit including first, second and third transistors having first terminals connected to a voltage source and having gate terminals coupled by way of a gate control line to at least one output node of the op-amp such that the first, second and third transistors are controlled to respectively pass first, second and third currents to first, second and third signal lines in response to an op-amp output signal generated by said op-amp and transmitted on said gate control line;a first stage coupled to said current mirror circuit and configured to generate a negative temperature dependent voltage in response to at least one of said first, second and third currents, said negative temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a second stage coupled to said current mirror circuit and configured to generate a positive temperature dependent voltage in response to at least one of one of said first, second and third currents, said positive temperature dependent voltage being coupled to at least one of said first and second op-amp input terminals;a third stage coupled to said current mirror circuit and configured to generate said reference voltage in accordance with at least one of the first, second and third currents; anda current chopping circuit connected to said first, second and third signal lines and configured to periodically alternately transmit said first, second and third currents to said first, second and third stages such that said first, second and third currents are respectively transmitted to said first, third and second stages during a first phase of a three-phase cycle, such that said first, second and third currents are respectively transmitted to said second, first and third stages during a second phase of a three-phase cycle, and such that said first, second and third currents are respectively transmitted to said third, first and second stages during a third phase of a three-phase cycle,wherein said current chopping circuit comprises a three-phase switching circuit connected between said first, second and third signal lines and said first, second and third stages and configured such that said first, second and third signal lines are respectively coupled to said first, third and second stages during said first phase of said three-phase cycle, such that said first, second and third signal lines are respectively coupled to said second, first and third stages during said second phase of said three-phase cycle, and such that said first, second and third signal lines are respectively coupled to said third, first and second stages during said third phase of said three-phase cycle, andwherein said current chopping circuit further comprises a ring counter circuit configured to generate a second clock signal, a third clock signal, and a fourth clock signal such that only said second clock signal is asserted during said first phase of said three-phase cycle, such that only said third clock signal is asserted during said second phase of the three phase cycle, and such that only said fourth clock signal is asserted during said third phase of said three phase cycle. 16. The BGR circuit of claim 15, wherein said three-phase switching circuit comprises: a first switch group including a first plurality of switches configured to couple the first signal line to said first stage during each said first phase of said three-phase cycle, to couple the first signal line to said second stage during each said second phase of said three-phase cycle, and to couple the first signal line to said third stage during each said third phase of said three-phase cycle;a second switch group including a second plurality of switches configured to couple the second signal line to said third stage during each said first phase of said three-phase cycle, to couple the second signal line to said first stage during each said second phase of said three-phase cycle, and to couple the second signal line to said second stage during each said third phase of said three-phase cycle; anda third switch group including a third plurality of switches configured to couple the third signal line to said second stage during each said first phase of said three-phase cycle, to couple the third signal line to said third stage during each said second phase of said three-phase cycle, and to couple the third signal line to said first stage during each said third phase of said three-phase cycle.
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