초록 ▼

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug m

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

대표청구항 ▼

1. An integrated circuit comprising: (a) first function and test circuitry having a test input and output;(b) second function and test circuitry having a test input and output;(c) a power pad;(d) demodulation circuitry having an input coupled to the power pad and an output;(e) modulation circuitry h

1. An integrated circuit comprising: (a) first function and test circuitry having a test input and output;(b) second function and test circuitry having a test input and output;(c) a power pad;(d) demodulation circuitry having an input coupled to the power pad and an output;(e) modulation circuitry having an output coupled to the power pad and an input; and(f) messaging and control circuitry having an input coupled to the output of the demodulation circuitry, an output coupled to the input of the modulation circuitry, a first test input and output coupled to the test input and output of the first function and test circuitry, and a second test input and output coupled to the test input and output of the second function and test circuitry. 2. The integrated circuit of claim 1 in which there are first and second power pads, and the demodulation circuitry has an input coupled to the first power pad and the modulation circuitry has an output coupled to the second power pad. 3. The integrated circuit of claim 1 in which the first function and test circuitry has a DC power input coupled to the power pad and the second function and test circuitry has a DC power input coupled to the power pad. 4. The integrated circuit of claim 1 in which the first function and test circuitry has a DC power input coupled to the power pad by first filter circuitry, and the second function and test circuitry has a DC power input coupled to the power pad by second filter circuitry. 5. The integrated circuit of claim 4 in which the first filter circuitry includes a first inductor coupled between the power pad and the DC power input of the first function and test circuitry and a first capacitor connected to between the first inductor and the DC power input of the first function and test circuitry and a ground pad, and the second filter circuitry includes a second inductor coupled between the power pad and the DC power input of the second function and test circuitry and a second capacitor connected to between the second inductor and the DC power input of the second function and test circuitry. 6. The integrated circuit of claim 1 in which there are first and second power pads, and the demodulation circuitry has an input coupled to the first power pad and the modulation circuitry has an output coupled to the second power pad, and in which the first function and test circuitry has a DC power input coupled to the first power pad and the second function and test circuitry has a DC power input coupled to the second power pad. 7. The integrated circuit of claim 1 in which there are first and second power pads, the demodulation circuitry has an input coupled to the first power pad and the modulation circuitry has an output coupled to the second power pad, and in which the first function and test circuitry has a DC power input coupled to the first power pad by first filter circuitry, and the second function and test circuitry has a DC power input coupled to the second power pad by second filter circuitry. 8. The integrated circuit of claim 7 in which the first filter circuitry includes a first inductor coupled between the first power pad and the DC power input of the first function and test circuitry and a first capacitor connected to between the first inductor and the DC power input of the first function and test circuitry and a ground pad, and the second filter circuitry includes a second inductor coupled between the second power pad and the DC power input of the second function and test circuitry and a second capacitor connected to between the second inductor and the DC power input of the second function and test circuitry. 9. The integrated circuit of claim 1 including a first capacitor coupling the input of the demodulation circuitry to the power pad, and a second capacitor coupling the output of the modulation circuitry to the power pad. 10. The integrated circuit of claim 1 in which there are first and second power pads, and including a first capacitor coupling the input of the demodulation circuitry to the first power pad, and a second capacitor coupling the output of the modulation circuitry to the second power pad.