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An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maxim

An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

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1. An apparatus for managing power on a System on a Chip, comprising: a power switch arbitrator configured to govern an arbitration between different power domains and a sequencing of powering up the different power domains supplied by a first voltage supply circuit on the System on a Chip, where th

1. An apparatus for managing power on a System on a Chip, comprising: a power switch arbitrator configured to govern an arbitration between different power domains and a sequencing of powering up the different power domains supplied by a first voltage supply circuit on the System on a Chip, where the power switch arbitrator has arbitration logic to arbitrate at approximately the same time and sequencing logic to limit a number of the different power domains simultaneously powering up to a maximum amount of domains, wherein powering up the maximum amount of power domains draws an amount of instantaneous electrical current from the first voltage supply circuit that is low enough to not cause a drop in voltage level below a minimum allowable supply voltage level for the first voltage supply circuit,where the sequencing logic of the power switch arbitrator is configured to provide the sequencing of powering up the different power domains that takes into account at least the following aspects of I) a first reference table or register configured to convey whether a first power domain and a second power domain arbitrating to power up a) are part of a set of power domains that share a same voltage domain powered by the first voltage supply circuit, and/or b) are powered from different voltage domains;II) a second reference table or register configured to convey a first amount of an instantaneous electrical current drawn by the first power domain to power up as well as a third reference table or register configured to convey a second amount of instantaneous electrical current drawn by the second power domain from the first voltage supply circuit, which both are either ‘factored into’ or ‘compared to’ a domain credits value from a fourth reference table or register configured to convey a predicted maximum amount instantaneous electrical current draw from the first voltage supply circuit before a reduction in voltage occurs below the minimum allowable supply voltage level for the first voltage supply circuit; andIII) a credit counter arrangement configured to manage a total amount of instantaneous electrical currently being drawn from the first voltage supply circuit from any power domains at the time period of when the first power domain and second power domain submit their arbitration requests to power up;where the sequencing logic is configured to allow the first power domain and second power domain to power up at the same time at a non-restricted power up rate as long as the supplied amount of instantaneous electrical current from the first voltage supply circuit is low enough to not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit;and when the first and second power domains powering up at the same time at the non-restricted power up rate would predictably cause an excessive amount of instantaneous electrical current to be drawn that would cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit, then the sequencing logic governs the power up sequencing to cause any one of the following three behaviors, based on programmed behaviors selected by a System on a Chip designer, i) the sequence logic delays in time sequentially waking up and powering up the second power domain after the first power domain so that a supply voltage level from the first voltage supply circuit does not drop below the minimum allowable supply voltage level for the first voltage supply circuit, orii) the sequence logic allows both the first and second power domains to power up, at the same time, at a limited electrical current draw rate set at an amount to not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit, oriii) the sequence logic allows the first power domain to power up at a substantially greater rate of charge than the second power domain for a staggered amount of time but a total draw of instantaneous electrical current between the first and second power domains powering up at the same time from the first voltage supply circuit will not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit. 2. The apparatus for managing power of claim 1, further comprising: a timer circuit configured to track when one or more power domains in the set of different power domains supplied by the first voltage supply circuit are in a state of powering up; and thus, tracks a summation of instantaneous electrical current draws over time from the different power domains in the set, which a total summation of electrical current draws that could affect supply voltage droop and cause the drop in the voltage level from the first voltage supply circuit to below the minimum allowable supply voltage level for the first voltage supply circuit, where the timer circuit is configured to supply feedback to affect the domain credits value from the fourth reference table or register that conveys the predicted maximum amount instantaneous electrical current draw from the first voltage supply circuit before the reduction in voltage occurs below the minimum allowable supply voltage level for the first voltage supply circuit. 3. The apparatus for managing power of claim 1, where the sequencing logic is configured to take into account both instantaneous electrical current as well as an additional aspect that has its own set of power domains that have that additional aspect in common, which then that additional aspect of the power domain is taken into account for arbitrating power up requests from all of the power domains on a system of a chip. 4. The apparatus for managing power of claim 1, where the sequencing logic also takes into account at least the following aspect of geography of the power domain arbitrating to power up relative to a physical location of other power domains arbitrating to power up at approximately same time; and thus, an algorithm employed by the sequencing logic of the power switch arbitrator factors in both of these conditions 1) an amount of neighboring power domains sharing a common resource with any of the power domains in the set that share the first voltage supply circuit, when those neighboring power domains are in a state of powering up, and 2) the total amount of instantaneous electrical current draw of power domains in the set of power domains that share the first voltage supply circuit wanting to be powered up at substantially a same point in time. 5. The apparatus for managing power of claim 4, where the sequencing logic is configured to reference a table or similar component, which is programmable by the System on a Chip designer, to include at least instantaneous electrical current draws of powering up each power domain, addresses of the power domains, and whether they neighbor each other. 6. The apparatus for managing power of claim 1, where a first instance of a power switch arbitrator is physically located in an electrical supply path in between a voltage regulator circuit of the first power domain and electrical loads of the first power domain. 7. The apparatus for managing power of claim 1, where the System on a Chip is partitioned into multiple power domains, where the System on a Chip has power rails of different width dimensions; and thus, different electrical current capacities, and a first instance of the power switch arbitrator actively controls a largest amount of instantaneous electrical current a first power rail can possibly experience without dropping below the minimum allowable supply voltage level for the first voltage supply circuit, and a second instance of the power switch arbitrator actively controls a largest amount of instantaneous electrical current a second power rail without dropping below a minimum allowable supply voltage level for a second voltage supply circuit, where the second power rail has a different width dimension than the first power rail. 8. A non-transitory machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the apparatus of claim 1, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representations of the apparatus. 9. The apparatus for managing power of claim 1, further comprising: a first event monitor located on the first power domain, which is configured to detect if that power domain has completely powered up and then convey an activity signal to the credit counter arrangement configured to convey the predicted total amount of instantaneous electrical currently being drawn from the first voltage supply circuit from any other power domains at the time period of when the first power domain and second power domain submit their arbitration requests to power up, so that this can then be used to generate signal to free up credits. 10. The apparatus for managing power of claim 1, where a first instance of the power switch arbitrator has a behavior register for the sequencing logic to reference, where the behavior register is programmable by the System-on-a-Chip designer to convey a desired behavior for the power up sequencing for the set of power domains, based on programmed behaviors selected by the System-on-a-Chip designer in the behavior register, where the selected behavior can have any one of the following three behaviors for the power domains in the set of power domains i) the sequence logic delays in time sequentially waking up and powering up the second power domain after the first power domain so that a supply voltage level from the first voltage supply circuit does not drop below the minimum allowable supply voltage level for the first voltage supply circuit, orii) the sequence logic allows both the first and second power domains to power up, at the same time, at a limited electrical current draw rate set at an amount to not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit when all of the power domains in the set power up simultaneously, oriii) the sequence logic allows the first power domain to power up at a substantially greater rate of charge than the second power domain for a staggered amount of time but a total draw of instantaneous electrical current between the first and second power domains powering up at the same time from the first voltage supply circuit will not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit. 11. The apparatus for managing power of claim 1, where a first instance of the power switch arbitrator has a behavior register for the sequencing logic to reference, where the behavior register is programmable by the System-on-a-Chip designer to convey a desired behavior for the power up sequencing for the set of power domains, based on programmed behaviors selected by the System-on-a-Chip designer in the behavior register, where an amount of power-up domain credits for two or more power up behaviors for a given power domain are issued, where in a first behavior, a greater amount of power-up domain credits are issued to allow a power domain to power up at a non-restricted charge rate from a lower state of operation, where in a second behavior, a lower amount of power-up domain credits are issued to allow a power domain to power up from a higher power state of operation to an even higher power state of operation, where in a third behavior, a lower amount of power-up domain credits are issued to allow a power domain to power up at a restricted charge rate for that power domain, where in a fourth behavior, the power switch arbitrator may return a different number of credits than requested, which could indicate a need to power up more slowly at the restricted charge rate for that power domain, where in a fifth behavior, the arbitrator may delay in time the powering up of one or more power-gated domains relative to other power-gated domains in the set of power-gated domains to limit an amount of the different power domains simultaneously powering up to a maximum amount, where in all behaviors, the power switch arbitrator is configured to draw an amount of instantaneous electrical current from the first voltage supply circuit that is low enough to not cause a drop in voltage below a minimum allowable supply voltage level for the first voltage supply circuit. 12. A method for a set of power-gated domains on a System on a Chip, comprising: using one or more power switch arbitrators to produce a power up sequence for the set of power-gated domains that are all powered from the same voltage supply source for the System on a Chip;arbitrating among the set of power-gated domains all powered from the same voltage supply source to grant one or more power domains permission to power up at the same time;managing an amount of domain credits for each voltage supply source, which has an assigned total amount of credits in its credit pool; where sequencing logic in a power switch arbitrator checks to see whether credits are available in the credit pool, where credits are deducted from the supply pool at a start of a power up for a power domain and then credits are returned to the supply pool either i) when the power up of the power domain is complete or ii) when a set threshold is exceeded on the way to the complete power up;issuing an amount of credits for two or more power up behaviors for a given power domain, where a greater amount of credits are issued to allow a power domain to power up at a non-restricted charge rate from a lower state of operation, and a lower amount of credits are issued to allow a power domain to power up from 1) a higher power state of operation including but not limited to i) a sleep state of operation, ii) a memory contents retention state of operation, and iii) other states where that power domain has not been completely powered off to 2) an even higher power state of operation, and the lower amount of credits are issued to allow a power domain to power up at a restricted charge rate for that power domain; where the arbitrator may return a different number of credits than requested, which could indicate a need to power up more slowly at a restricted charge rate for that power domain;powering up one or more of the power-gated domains simultaneously from the lower power state of operation to the higher power state of operation or the even higher power state of operation;delaying in time the powering up of one or more power-gated domains relative to other power-gated domains in the set of power-gated domains to limit a number of the different power domains simultaneously powering up to a maximum amount of domains, wherein powering up the maximum amount of power domains draws an amount of instantaneous electrical current from a same voltage supply circuit that is low enough to not cause a drop in voltage level below a minimum allowable supply voltage level for the same voltage supply circuit; andwhere the System on a Chip has two or more voltage supply sources each supplying a different nominal voltage level, and where the two or more voltage supply sources may be arbitrated in parallel with each other. 13. The method of claim 12, where the power switch arbitrator also considers what priority is associated with a first domain in the set of power domains in a programmable relative priority scheme, where credits are reserved for latency-sensitive domains to ensure they do not get blocked. 14. The method of claim 12, where the power switch arbitrator avoids power up starvation of domains via use of a round robin arbitration scheme. 15. A method for managing power on a System on a Chip, comprising: governing an arbitration between different power domains at approximately the same time;sequencing powering up of the different power domains supplied by a first voltage supply circuit on the System on a Chip;limiting a number of the different power domains simultaneously powering up to a maximum amount of domains, wherein powering up the maximum amount of power domains draws an amount of instantaneous electrical current from the first voltage supply circuit that is low enough to not cause a drop in voltage level below a minimum allowable supply voltage level for the first voltage supply circuit;governing the sequencing of powering up the different power domains that takes into account at least the following aspects of i) whether a first power domain and a second power domain arbitrating to power up i) are part of a set of power domains that share a same voltage domain powered by the first voltage supply circuit, and/or ii) are powered from different voltage domains;ii) a first amount of an instantaneous electrical current drawn by the first power domain to power up as well as a second amount of instantaneous electrical current drawn by the second power domain from the first voltage supply circuit, which both are either ‘factored into’ or ‘compared to’ a domain credits value that corresponds to a predicted maximum amount instantaneous electrical current draw from the first voltage supply circuit before a reduction in voltage occurs below the minimum allowable supply voltage level for the first voltage supply circuit; andiii) manage a total amount of instantaneous electrical currently being drawn from the first voltage supply circuit from any power domains at the time period of when the first power domain and second power domain submit their arbitration requests to power up;allowing the first power domain and second power domain to power up at the same time at a non-restricted power up rate as long as the supplied amount of instantaneous electrical current from the first voltage supply circuit is low enough to not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit;and when the first and second power domains powering up at the same time at the non-restricted power up rate would predictably cause an excessive amount of instantaneous electrical current to be drawn that would cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit, then governing the power up sequencing to cause any one of the following three behaviors, based on programmed behaviors selected by a System on a Chip designer, i) delay in time sequentially waking up and powering up the second power domain after the first power domain so that a supply voltage level from the first voltage supply circuit does not drop below the minimum allowable supply voltage level for the first voltage supply circuit, orii) allow both the first and second power domains to power up, at the same time, at a limited electrical current draw rate set at an amount to not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit, oriii) allow the first power domain to power up at a substantially greater rate of charge than the second power domain for a staggered amount of time but a total draw of instantaneous electrical current between the first and second power domains powering up at the same time from the first voltage supply circuit will not cause the drop in voltage level to below the minimum allowable supply voltage level for the first voltage supply circuit. 16. The method for managing power of claim 15, further comprising: tracking when one or more power domains in the set of different power domains supplied by the first voltage supply circuit are in a state of powering up; and thus, tracking a summation of instantaneous electrical current draws over time from the different power domains in the set, which a total summation of electrical current draws of could affect supply voltage droop and cause the drop in the voltage level from the first voltage supply circuit to below the minimum allowable supply voltage level for the first voltage supply circuit; andsupplying feedback to affect the domain credits value that corresponds to the predicted maximum amount instantaneous electrical current draw from the first voltage supply circuit before the reduction in voltage occurs below the minimum allowable supply voltage level for the first voltage supply circuit. 17. The method for managing power of claim 15, further comprising: when arbitrating, taking into account at least the following aspect of geography of the power domain arbitrating to power up relative to a physical location of other power domains arbitrating to power up at approximately same time; and thus, factoring in both of these conditions 1) an amount of neighboring power domains sharing a common resource with any of the power domains in the set that share the first voltage supply circuit, when those neighboring power domains are in a state of powering up, and 2) the total amount of instantaneous electrical current draw of power domains in the set of power domains that share the first voltage supply circuit wanting to be powered up at substantially a same point in time. 18. A non-transitory machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the method of claim 15, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representations of the apparatus. 19. An apparatus, comprising: an arbitrator circuit configured to govern an arbitration between different power domains and sequence powering up the different power domains supplied by the same voltage supply circuit on a System on a Chip, where the arbitrator circuit utilizes sequencing logic to limit a number of the different power domains simultaneously powering up to a maximum amount of domains, wherein powering up the maximum amount of power domains draws an amount of instantaneous electrical current from a same voltage supply circuit that is low enough to not cause a drop in voltage level below a minimum allowable supply voltage level for the same voltage supply circuit, where the sequencing logic is configured to manage the sequencing of powering up the different power domains by taking into account multiple aspects including i) whether different power domains arbitrating to power up are part of a set of power domains that share the same voltage supply circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of domain credits before a reduction in voltage occurs below the minimum allowable supply voltage level for that same voltage supply circuit, where the sequencing logic of the power switch arbitrator is further configured to select a power up sequencing behavior from two or more power up sequencing behaviors using domain credits for powering up different power domains, where the amount of domain credits for each voltage supply source are managed such that the sequencing logic in the power switch arbitrator checks to see whether credits are available in the credit pool.