[특허]System and method for low distortion capacitive signal source amplifier

System and method for low distortion capacitive signal source amplifier 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03F-003/183 H04R-019/00 H04R-003/00 H03F-001/32 H04R-019/04 H03F-001/56 H03F-003/187
출원번호	US-0935072 (2015-11-06)
등록번호	US-10171046 (2019-01-01)
발명자 / 주소	Kropfitsch, Michael Ceballos, Jose Luis
출원인 / 주소	INFINEON TECHNOLOGIES AG
대리인 / 주소	Slater Matsil, LLP
인용정보	피인용 횟수 : 0 인용 특허 : 41

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According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting

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1. A method comprising: amplifying a signal provided by a capacitive signal source to form an amplified signal;detecting a peak voltage of the amplified signal;comparing the detected peak voltage to a predetermined threshold; andadjusting a controllable bias voltage of the capacitive signal source in response to detecting the peak voltage, the controllable bias voltage of the capacitive signal source being adjusted to a value inversely proportional to the detected peak voltage, wherein adjusting the controllable bias voltage comprises decreasing the controllable bias voltage at a first rate if the detected peak voltage exceeds the predetermined threshold, andincreasing the controllable bias voltage at a second rate if detected peak voltage does not exceed the predetermined threshold, wherein the first rate is greater than the second rate. 2. The method of claim 1, wherein: the capacitive signal source comprises a MEMS microphone; andthe controllable bias voltage is controlled such that a total harmonic distortion of the amplified signal is less than 10% for a 140dBSPL acoustic input to the MEMS microphone. 3. A system for amplifying a signal provided by a capacitive signal source, the system comprising: a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;a controllable bias circuit configured to be coupled to a bias node of the capacitive signal source, the controllable bias circuit configured to provide a controllable bias voltage to the capacitive signal source;a signal detection circuit coupled to an output of the signal amplifier, the signal detection circuit configured to detect peak signal values at the output of the signal amplifier; anda control circuit coupled between the signal detection circuit and the controllable bias circuit, the control circuit configured to adjust the controllable bias circuit in response to changes in detected peak signal values, and command the controllable bias circuit to decrease controllable bias voltage at a first rate if the signal detection circuit detects a peak signal level greater than a threshold, andincrease the controllable bias voltage at a second rate if the signal detection circuit does not detect a peak signal level greater than the threshold, wherein the first rate is greater than the second rate. 4. The system of claim 3, wherein the controllable bias circuit comprises: a digital-to-analog converter (DAC) coupled to an output of the control circuit; anda charge pump circuit coupled to an output of the DAC; anda lowpass filter coupled between the charge pump circuit and an output of the controllable bias circuit. 5. The system of claim 3, further comprising the capacitive signal source. 6. The system of claim 5, wherein the capacitive signal source comprises a MEMS microphone. 7. An integrated circuit for amplifying a signal provided by a capacitive signal source, the integrated circuit comprising: a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;a controllable bias circuit configured to be coupled to a bias node of the capacitive signal source at a first output terminal of the controllable bias circuit, the controllable bias circuit configured to provide a controllable bias voltage to the capacitive signal source via the first output terminal;a peak detector coupled to an output of the signal amplifier;a comparator coupled to an output of the peak detector and the output of the signal amplifier, the comparator configured to compare an output of the peak detector with a threshold; anda control circuit coupled between the an output of the comparator and a control input of the controllable bias circuit, wherein the control circuit is configured to command the controllable bias circuit to adjust the controllable bias circuit in response to changes in detected peak signal values, command the controllable bias circuit to decrease controllable bias voltage at a first rate if the peak detector detects a peak signal level greater than the threshold and increase the controllable bias voltage at a second rate if the peak detector does not detect a peak signal level greater than the threshold, wherein the first rate is greater than the second rate. 8. The integrated circuit of claim 7, wherein the control circuit comprises: a counter coupled to the output of the comparator, the counter being configured to increment if the output of the peak detector exceeds the threshold and decrement if the output of the peak detector does not exceed the threshold; anda look-up table circuit coupled to the output of the counter. 9. The integrated circuit of claim 7, wherein: the integrated circuit further comprises a single-ended to differential conversion circuit coupled between the signal amplifier and the peak detector;the peak detector comprises a positive peak detector and a negative peak detector; andthe comparator comprises a differential comparator configured to compare an output of the positive peak detector with a positive threshold, and an output of the negative peak detector with a negative threshold. 10. The integrated circuit of claim 7, further comprising a zero crossing detector coupled to the output of the signal amplifier, wherein the control circuit is configured to adjust the controllable bias circuit when the zero crossing detector detects a zero crossing. 11. The integrated circuit of claim 7, wherein the controllable bias circuit comprises: a digital-to-analog converter (DAC) coupled to an output of the control circuit,a charge pump circuit coupled to an output of the DAC, anda lowpass filter coupled between the charge pump circuit and the first output terminal of the controllable bias circuit.

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