Predictive scheduler for memory rank switching
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/06
G11C-011/4091
G11C-011/406
출원번호
US-0659863
(2017-07-26)
등록번호
US-10175893
(2019-01-08)
발명자
/ 주소
Bonanno, James J.
Cadigan, Jr., Michael J.
Collura, Adam B.
Lipetz, Daniel
Meaney, Patrick J.
Walters, Craig R.
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Paskalov, Dmitry
인용정보
피인용 횟수 :
0인용 특허 :
19
초록▼
Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks ar
Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.
대표청구항▼
1. A method for scheduling memory accesses in a memory system, wherein the memory system is a multi-rank dynamic random access memory (DRAM) system having a plurality of ranks of memory, at most a total of r ranks is powered up concurrently, wherein r is less than the plurality of ranks, the method
1. A method for scheduling memory accesses in a memory system, wherein the memory system is a multi-rank dynamic random access memory (DRAM) system having a plurality of ranks of memory, at most a total of r ranks is powered up concurrently, wherein r is less than the plurality of ranks, the method comprising: in response to determining that fewer than r ranks are powered up, wherein the determining that fewer than r ranks are powered up is performed in response to a clock period, wherein the clock period is one of: a clock cycle or a memory cycle, and wherein determining that fewer than r ranks are powered up comprises powering up a subset of requested powered down ranks of the plurality of ranks, such that the at most a total of r ranks is powered up concurrently, wherein the subset of requested powered down ranks of the plurality of ranks to be powered up comprises a most frequently accessed requested powered down ranks of the plurality of ranks, wherein each of the most frequently accessed requested powered down ranks of the plurality of ranks is based on a number of memory requests received within a defined time window for that rank, respectively, wherein for each rank of the plurality of ranks the defined time window corresponds to an interval of time during which the rank has received a sequence of memory requests based on a respective AC value and wherein the respective AC value is an active count number, determined based on a number of memory requests received by the requested powered down ranks of the plurality of ranks; and thenin response to determining that fewer than the r ranks are powered up, powering up a subset of unrequested powered down ranks of the plurality of ranks, such that the at most a total of r ranks is powered up concurrently, wherein the subset of unrequested powered down ranks of the plurality of ranks to be powered up comprises a most frequently accessed unrequested powered down ranks of the plurality of ranks, wherein each of the most frequently accessed unrequested powered down ranks of the plurality of ranks is based on the number of memory requests received within the defined time window for that rank, respectively, wherein for each rank of the plurality of ranks the defined time window corresponds to the interval of time during which the rank has received a sequence of memory requests based on a respective X value, and wherein the respective X value is a positive integer determined based on the respective AC value.
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이 특허에 인용된 특허 (19)
Madrid, Philip E.; Askar, Tahsin, Detection of speculative precharge.
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Burton, David Alan; Webman, Erez, Method, system, and program for demoting data from cache based on least recently accessed and least frequently accessed data.
Stacovsky, Henry; Szabelski, Piotr, Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus.
Harriman David J. ; Langendorf Brain K. ; Riesenman Robert J., System for issuing a command to a memory having a reorder module for priority commands and an arbiter tracking address of recently issued command.
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