A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with re
A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.
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1. A memory system comprising: a nonvolatile memory device including a data area and a device information area, the device information area being inaccessible by a host; anda controller configured to perform a training operation with respect to a data signal transmitted to or received from the nonvo
1. A memory system comprising: a nonvolatile memory device including a data area and a device information area, the device information area being inaccessible by a host; anda controller configured to perform a training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area, the controller being configured to select a selected one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation and the second training operation such that, the first training operation is performed based on a rooted training code generated by the controller, wherein the first training operation is a rooted training operation that includes checking all sections of the data signal based on the rooted training code including all training codes within a training range, andthe second training operation is performed based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation, wherein the second training operation is a mirror training operation that includes checking only some of the sections of the data signal based on the dynamic training code. 2. The memory system of claim 1, wherein the controller is configured to perform the first training operation in response to the identification code being an initial identification code. 3. The memory system of claim 2, wherein the controller is configured to change the initial identification code to a post identification code for performing the second training operation, and store the post identification code in the device information area, after the controller completes the first training operation. 4. The memory system of claim 3, wherein the controller is configured to perform the second training operation in response to the identification code being the post identification code. 5. The memory system of claim 1, wherein the mirror training operation includes checking a section of the data signal corresponding to a training code spaced a specific interval apart from the dynamic training code and searching a center of the data signal according to a checking result. 6. The memory system of claim 4, wherein the controller is configured to update the identification code and the dynamic training code in the device information area after the controller completes the second training operation. 7. The memory system of claim 1, wherein the controller includes a training management unit configured to manage the identification code and the dynamic training code, the training management unit comprising: an identification code register configured to temporarily store the identification code;a training code register configured to temporarily store the dynamic training code;a multiplexer configured to output one of the rooted training code and the dynamic training code of the training code register according to the identification code of the identification code register;a training delay control circuit configured to perform the selected one of the first training operation and the second training operation based on an output value of the multiplexer; anda training code update circuit configured to update the identification code and the dynamic training code in the device information area based on a result value of the selected one of the first training operation and the second training operation performed by the training delay control circuit. 8. A memory system comprising: a nonvolatile memory device including a data area and a device information area, the device information area being inaccessible by a host;a dynamic random access memory configured to temporarily store data received from the host and data read from the nonvolatile memory device; anda controller configured to perform a DRAM training operation with respect to a data signal transmitted to or received from the dynamic random access memory based on DRAM training information stored in the device information area, the controller being configured to select a selected one of a first DRAM training operation and a second DRAM training operation based on a DRAM identification code of the DRAM training information, and to perform the selected one of the first DRAM training operation and the second DRAM training operation such that, the first DRAM training operation is performed based on a DRAM rooted training code generated by the controller, wherein the first DRAM training operation is a DRAM rooted training operation that includes checking all sections of the data signal based on the DRAM rooted training code including all training codes within a training range, andthe second DRAM training operation is performed based on a DRAM dynamic training code of the DRAM training information, the second DRAM training operation including performing a fewer number of searches than the first DRAM training operation, wherein the second DRAM training operation is a DRAM mirror training operation that includes checking only some of the sections of the data signal based on the DRAM dynamic training code. 9. The memory system of claim 8, wherein the controller is configured to perform the first DRAM training operation in response to the DRAM identification code being an initial DRAM identification code. 10. The memory system of claim 9, wherein the controller is configured to perform the second DRAM training operation in response to the DRAM identification code being a post DRAM identification code. 11. The memory system of claim 8, wherein the nonvolatile memory device includes a ZQ management unit configured to selectively perform one of a first ZQ calibration operation and a second ZQ calibration operation based on ZQ calibration information stored in the device information area, wherein the ZQ calibration information includes a ZQ identification code. 12. The memory system of claim 11, wherein the ZQ management unit is configured to perform the first ZQ calibration operation, in response to the ZQ identification code being an initial ZQ identification code, based on a ZQ initial calibration code generated by the ZQ management unit. 13. The memory system of claim 12, wherein the ZQ management unit is configured to perform the second ZQ calibration operation, in response to the ZQ identification code being a post ZQ identification code, based on a ZQ dynamic calibration code of the ZQ calibration information. 14. A controller configured to communicate with one or more of a nonvolatile memory device and a dynamic random access memory, the nonvolatile memory device including a data area and a device information area, the device information area storing training information and being inaccessible by a host, and the dynamic random access memory configured to temporarily store data received from the host and data read from the nonvolatile memory device, the controller comprising: at least one processor configured to selectively perform one or more of a rooted training operation and a mirror training operation with respect to at least one data signal based on the training information stored in the device information area, the at last one data signal being transmitted to or received from at least one of the nonvolatile memory device and the dynamic random access memory, the training information including one or more of an NVM identification code and a DRAM identification code, the mirror training operation including performing a fewer number of searches than the rooted training operation. 15. The controller of claim 14, wherein: the at least one processor is configured to selectively perform the rooted training operation by performing at least one of, an NVM rooted training operation based on an NVM rooted training code generated by the controller in response to the training information including an initial NVM identification code, anda DRAM rooted training operation based on a DRAM rooted training code generated by the controller in response to the training information including an initial DRAM identification code; andthe at least one processor is configured to selectively perform the mirror training operation by performing at least one of, an NVM mirror training operation based on an NVM dynamic training code of the training information in response to the training information including a post NVM identification code, anda DRAM mirror training operation based on a DRAM dynamic training code of the training information in response to the training information including a post DRAM identification code. 16. The controller of claim 15, wherein the at least one processor is configured to selectively perform, the NVM rooted training operation by checking all sections of the at least one data signal based on the NVM rooted training code including all NVM training codes within an NVM training range,the DRAM rooted training operation by checking all sections of the at least one data signal based on the DRAM rooted training code including all DRAM training codes within a DRAM training range,the NVM mirror training operation by checking only some of the sections of the at least one data signal based on the NVM dynamic training code, wherein the NVM mirror training operation includes checking a section of the at least one data signal corresponding to an NVM training code spaced a specific interval apart from the NVM dynamic training code and searching a center of the at least one data signal according to an NVM checking result, andthe DRAM mirror training operation by checking only some of the sections of the at least one data signal based on the DRAM dynamic training code, wherein the DRAM mirror training operation includes checking a section of the at least one data signal corresponding to a DRAM training code spaced a specific interval apart from the DRAM dynamic training code and searching a center of the at least one data signal according to a DRAM checking result. 17. The controller of claim 16, wherein the at least one processor is further configured to, change the initial NVM identification code to the post NVM identification code for performing the NVM mirror training operation, and store the post NVM identification code in the device information area, after completing the NVM rooted training operation,change the initial DRAM identification code to the post DRAM identification code for performing the DRAM mirror training operation, and store the post DRAM identification code in the device information area, after completing the DRAM rooted training operation,update the NVM identification code and the NVM dynamic training code of the training information in the device information area after completing the NVM mirror training operation, andupdate the DRAM identification code and the DRAM dynamic training code of the training information in the device information area after completing the DRAM mirror training operation. 18. The controller of claim 14, wherein, the device information area further stores ZQ calibration information, wherein the ZQ calibration information includes a ZQ identification code, andthe nonvolatile memory device is configured to selectively perform at least one ZQ calibration operation based on the ZQ calibration information stored in the device information area, wherein the nonvolatile memory device is configured to selectively perform one or more of, a first ZQ calibration operation based on a ZQ initial calibration code generated in response to the ZQ identification code being an initial ZQ identification code, anda second ZQ calibration operation based on a ZQ dynamic calibration code of the ZQ calibration information in response to the ZQ identification code being a post ZQ identification code, wherein the nonvolatile memory device is further configured to, change the initial ZQ identification code to the post ZQ identification code for performing the second ZQ calibration operation, and store the post ZQ identification code in the device information area, after completing the first ZQ calibration operation, andupdate the ZQ identification code and the ZQ dynamic calibration code in the device information area after completing the second ZQ calibration operation.
Yoon, Chi Weon; Chae, Donghyuk; Park, Jae-Woo; Nam, Sang-Wan, Nonvolatile memory device, operating method thereof and memory system including the same.
Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K.; Buyuktosunoglu, Alper, Three-dimensional processing system having independent calibration and statistical collection layer.
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