A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels,
A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.
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1. A register clock driver (RCD), comprising: a logic having one or more input channels, each of the one or more input channels receiving input signals; anda plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on eac
1. A register clock driver (RCD), comprising: a logic having one or more input channels, each of the one or more input channels receiving input signals; anda plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals,wherein the RCD is configured to operate in one of a default mode or a non-default mode,wherein in the default mode the input signals are provided to each of the plurality of output ports, andwherein in the non-default mode, when an RD, WR, or WR Z command is received on a channel of the one or more input channels, in a first rank a first set of input signals is coupled to a first port, a first portion of the first set of input signals is coupled to a second port, and a first remainder of signals on the second port is set to high. 2. The RCD of claim 1, wherein in a dual rank system, the logic provides the input signals from a first channel of the one or more input channels to a first ranked first channel output port of the plurality of ranked output ports when a first rank is received and couples the input signals from the first channel to a second ranked first channel output port of the plurality of ranked output ports when a second rank is received. 3. The RCD of claim 1, wherein in a single rank system, input signals from each of the one or more input channels is provided to one port of the plurality of ports associated with each of the one or more input channels. 4. The RCD of claim 1, wherein in a quad rank system, input signals from each of the one or more input channels is provided to output ports associated with the input channel and the rank. 5. The RCD of claim 1, wherein in non-default mode in the RD, WR, or WR_Z command, in the first rank, a second set of input signals is coupled to the first portion, a second portion of the second set of input signals is coupled to the second port, and a second remainder of signals on the second port are set to high. 6. The RCD of claim 1, wherein in non-default mode at least some commands received on a channel of the one or more input channels are provided to all of the plurality of ranked output ports associated with the channel. 7. The RCD of claim 1, wherein in non-default mode at least commands received on a channel of the one or more input channels are provided to a port of the plurality of output ports associated with a rank. 8. The RCD of claim 1, wherein in an idle state signals on each of the plurality of output ports are set to high so as to reduce power. 9. The RCD of claim 1, wherein the one or more input channels includes a first channel and a second channel and the plurality of ranked output ports includes a first port associated with the first channel, a second port associated with the first channel, a third port associated with the second channel and a fourth port associated with the second channel; and wherein the logic receives input signals from the first channel and couples the input signals to the first port for a first rank, and couples the input signal to the second port for a second rank; and wherein the logic receives signals from the second channel and couples the input signals to the third port for the first rank, and couples in the input signal to the fourth port for the second rank. 10. The RCD of claim 1, further including an address bus inversion function to maximize a count of high signals. 11. The RCD of claim 1, further including memory coupled to the plurality of ranked output ports. 12. A method of operating a memory module, comprising: receiving in a register clock driver (RCD) first signals on a first channel;outputting the first signals from the RCD on a first port associated with the first channel for a first rank; andoutputting the first signals from the RCD on a second port associated with the first channel for a second rank,wherein the RCD is configured to operate in one of a default mode or a non-default mode,wherein in the default mode the input signals are provided to each of the plurality of output ports, and wherein in the non-default mode, when an RD, WR, or WR Z command is received on a channel of the one or more input channels, in a first rank a first set of input signals is coupled to a first port, a first portion of the first set of input signals is coupled to a second port, and a first remainder of signals on the second port is set to high. 13. The method of claim 12, further comprising: receiving in the RCD second signals on a second channel;outputting the second signals from the RCD on a first port associated with the second channel for the first rank; andoutputting the second signals from the RCD on a second port associated with the second channel for the second rank. 14. The method of claim 13, wherein during an idle state, signals on the first port and the second port are held at a high state. 15. The method of claim 13, further including receiving command signals on the first channel;if the command signals are for a read or write command, directing the command signals to the first port for the first rank or directing the command signals to the second port for the second rank; andif the command signals are not for the read or write command, directing a subset of the command signals to the second port for the first rank or directing the subset of the command signals to the first port for the second rank;holding unused output signals from the first port or the second port at a high state. 16. The method of claim 13, further including receiving command signals on the first channel;directing the command signals to the first port for the first rank or the second port for the second rank; andholding unused outputs signals from the first port or the second port at a high state. 17. The method of claim 13, further including receiving command signals on the first channel; anddirecting the command signals to both the first port and the second port.
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