RDMA-SSD dual-port unified memory and network controller
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/06
G11C-014/00
G06F-013/38
G06F-013/40
H04L-029/08
G06F-012/02
G06F-012/0868
G11C-013/00
출원번호
14644021
(2015-03-10)
등록번호
10453530
(2019-10-22)
발명자
/ 주소
Lee, Xiaobing
Young, Michael
Li, Ting
Wang, Yansong
Chen, Yong
출원인 / 주소
Futurewei Technologies, Inc.
대리인 / 주소
Schwegman Lundberg & Woessner, P.A.
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA
System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs.
대표청구항▼
1. A non-volatile memory express (NVME) controller comprising: two host interfaces separate from each other, with one of the two host interfaces configured for communications with a host processor and the other one of the two host interfaces configured for communications with another host processor;
1. A non-volatile memory express (NVME) controller comprising: two host interfaces separate from each other, with one of the two host interfaces configured for communications with a host processor and the other one of the two host interfaces configured for communications with another host processor;a dual port fabric port configured for peer communication;a dual port unified memory interface configured for communication with dynamic memories and nondeterministic persistent memories and a plurality of dual-port non-volatile storage modules;a memory cache comprising a first volatile memory, a second volatile memory, and a non-volatile memory with the non-volatile memory being physically distinct and separate from the first and second volatile memories, and the first and second volatile memories being physically distinct and separate from each other; andtwo processors communicatively coupled with the two host interfaces, the dual port fabric port, the unified memory interface, and the memory cache, with one of the two processors coupled to the first volatile memory via a first bus and the other one of the two processors coupled to the second volatile memory via a second bus, the two processors coupled to the non-volatile memory with the non-volatile memory dedicated and coupled to each of the two processors separate from the first and second buses coupling the two processors to the first and second volatile memories, the two processors configured to store data in the memory cache, shared by the two processors, in response to a data request received at one of the dual port fabric port and one of the two host interfaces, the first and second volatile memories arranged for read caching and the non-volatile memory arranged for write caching to provide a copy of the data while the data is being prepared for storage in a primary storage and for metadata caching, and the two processors configured to determine a non-volatile storage module of a dual-port all-flash array (AFA) for the data associated with the data request, the non-volatile storage module in communication with the unified memory interface and associated with the data request, wherein each processor of the two processors has independent control of the plurality of dual-port non-volatile storage modules;wherein the NVME controller is operable as part of a NVME storage node to allow a remote data memory access (RDMA) write into the memory cache from other NVME storage nodes, including using N+M error coding, where M is a positive integer that is a redundancy factor for the N+M error coding and N+M equals a total number of non-volatile storage modules of the dual-port AFA associated with one or both of the two processors. 2. The NVME controller according to claim 1, wherein each of the two processors is configured to communicate, after a data block is cached in the non-volatile memory, that the data request being a write request is completed and committed and then store the data block to be written to the non-volatile storage module later on. 3. The NVME controller according to claim 1, wherein the data stored in response to the data request is stored in the first volatile memory or the second volatile memory via remote direct memory access. 4. The NVME controller according to claim 3, wherein the data stored in the first volatile memory or the second volatile memory is also cached into the non-volatile memory for a configurable, given period of time. 5. The NVME controller according to claim 1, wherein the data comprises a header and a payload, and wherein the header is forwarded on the first bus to the first volatile memory or on the second bus to the second volatile memory and the payload is forwarded on a third bus to the non-volatile storage module. 6. The NVME controller according to claim 1, further comprising a plurality of dual port fabric ports communicatively coupled to a respective plurality of NVME controllers, accessible by multiple pairs of hosts. 7. The NVME controller according to claim 1, further comprising more than two processors and more than two host interfaces. 8. A non-volatile memory express (NVME) storage node comprising: two host processors;a switch fabric;a dual-port non-volatile storage all-flash array module (AFA DIMM); anda NVME controller, comprising: two host interfaces communicatively coupled to other two host processors in different nodes;a dual port switch fabric port communicatively coupled to the switch fabric;a unified memory interface communicatively coupled to the dual-port non-volatile storage all-flash array module;a memory cache having volatile memory for reads and non-volatile memory for writes and metadata, the volatile memory being physically distinct and separate from the non-volatile memory; anda processor communicatively coupled with the two host interfaces, the dual port switch fabric port, the unified memory interface and the memory cache, the processor configured to store data in the memory cache in response to a data request received at one of the dual port fabric port and one of the two host interfaces, the volatile memory of the memory cache arranged for read caching via a bus coupled to the processor and the non-volatile memory of the memory cache arranged for write caching to provide a copy of the data while the data is being prepared for storage in a primary storage and for metadata caching, the non-volatile memory of the memory cache dedicated and coupled to each of the processor and another processor of the NVME controller, the non-volatile memory coupled separate from the bus coupling the volatile memory to the processor, and the processor to subsequently modify the data in the dual-port non-volatile storage all-flash array module (AFA DIMM) according to the request;wherein the NVME storage node is operable to allow a remote data memory access (RDMA) write into the memory cache from other NVME storage nodes, including using N+M error coding, where M is a positive integer that is a redundancy factor for the N+M error coding and N+M equals a total number of AFA DIMMs of the NVME storage node associated with the processor. 9. The NVME storage node according to claim 8, wherein the volatile memory comprises dynamic random-access memory (DRAM) and the non-volatile memory comprises magnetoresistive random-access memory (MRAM). 10. The NVME storage node according to claim 9, wherein a unified memory bus comprises a first data bus in communication with the DRAM, and a second data bus in communication with the dual-port non-volatile storage all-flash array module. 11. The NVME storage node according to claim 8, wherein a plurality of dual port all-flash array (AFA) non-volatile storage modules in DIMM form factor comprises the dual port non-volatile storage all-flash array module (AFA DIMM). 12. The NVME storage node according to claim 11 comprising at least two host processors and at least two NVME controllers, wherein the data request received at a first NVME controller of the at least two NVME controllers is copied and forwarded to a second memory cache of the second NVME controller of the at least two NVME controllers, and the at least two host processors can access any of a plurality of dual port non-volatile storage all-flash array modules. 13. The NVME storage node of claim 8, wherein the unified memory interface comprises a 64bit DDR4 bus split into 8bit DDR4-ONFI channels. 14. The NVME storage node according to claim 8, wherein the non-volatile memory express (NVME) storage node is based on dual-port fabric and plurality of dual-port storage modules AFA DIMM devices that not only provide a redundant secondary data access path but also double the data throughput as needed by applications, as flash storages over dual-port DDR memory channels. 15. A method for directing a data request to an all-flash array (AFA), the method comprising: receiving a data request at a host processor to modify data in an all-flash array (AFA);determining, by the host processor, a non-volatile memory (NVM) storage node associated with the data request;storing the data in a memory cache having a volatile memory and a non-volatile memory, such that the volatile memory of the memory cache is arranged for read caching the data coupled via a bus and the non-volatile memory of the memory cache is arranged for write caching to provide a copy of the data while the data is being prepared for storage in a primary storage, the non-volatile memory of the memory cache dedicated and coupled to each of a first processor and a second processor of a non-volatile memory express (NVME) controller on which the memory cache is disposed, the non-volatile memory coupled separate from the bus coupling the volatile memory to the processor, the non-volatile memory coupled to cache the data;forwarding the data request to the NVME controller;transmitting the data request to a storage module of the AFA through a memory control bus shared by multiple dual-port AFA DIMM devices; thenwriting the data as data blocks into each AFA DIMM device through eight of an eight-bit DDR4 data sub-channels for parallel block writes, or fetching the data as data blocks from each AFA DIMM device by the controller as parallel block reads; andallowing a remote data memory access (RDMA) write into the memory cache from other NVM storage nodes, including using N+M error coding, where M is a positive integer that is a redundancy factor for error coding and N+M equals a total number of dual-port AFA DIMM devices associated with the first processor or the second processor. 16. The method of claim 15, wherein the storing the data includes buffering a data block that comprises a remote data memory access (RDMA) by an agent generating the data block in the non-volatile memory of the memory cache for writes then the NVME controller direct memory access (DMA) writing this data block into one of storage AFA DIMM at a later time. 17. The method of claim 15, wherein the data request comprises a read request, and the data request is assigned to one of the dual-port AFA DIMM devices for block read operations; then this data block is buffered in a dynamic random-access memory (DRAM) cache for local host or remote data memory access (RDMA) hosts. 18. The method of claim 17, wherein the data request is stored in the DRAM cache for a configurable, given time period, for future cache-hit reads without accessing flash storages. 19. The method of claim 15, wherein the data request is a write request, and the data request is stored in a magnetoresistive random-access memory (MRAM) cache. 20. The method of claim 19, wherein the data request is initially stored in a DRAM cache. 21. The method according to claim 15, wherein the NVME controller is in communication with a second NVME controller of a second NVM storage node of a distributed data network, and wherein the data is stored in one of a volatile and a non-volatile memory cache of the second NVM storage node. 22. A non-volatile memory express (NVME) storage node comprising: a host processor;a switch fabric;a dual-port non-volatile storage all-flash array module (AFA DIMM); anda NVME controller comprising: a host interface communicatively coupled to the host processor;a dual port switch fabric port communicatively coupled to the switch fabric;a unified memory interface communicatively coupled to the dual-port on-volatile storage all-flash array module;a memory cache having volatile memory for reads and non-volatile memory for writes and metadata; anda processor communicatively coupled with the host interface, the dual port switch fabric port, the unified memory interface and the memory cache, the processor configured to store data in the memory cache in response to a data request received at one of the host interface and the dual port fabric port, and to subsequently modify the data in the dual-port non-volatile storage all-flash array module (AFA DIMM) according to the request, wherein the NVME storage node is in communications with other available NVME storage nodes to allow the other available NVME storage nodes to remote data memory access (RDMA) write suitable data blocks or parity blocks into DRAM buffers of the NVME storage node, in order to recover a lost data block or failed to read from the NVME storage node; wherein with a number of redundant parity blocks being variable m and a number of protected data blocks being N, N+m is selected to be less than a total number of the dual-port AFA DIMM devices distributed within all the NVME storage nodes.
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