[미국특허]
Measuring current in a constant on-time regulator
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02M-001/14
H02M-001/088
G01R-019/00
H02M-003/155
H02M-001/00
출원번호
16523374
(2019-07-26)
등록번호
11336168
(2022-05-17)
발명자
/ 주소
Shao, Bin
출원인 / 주소
NXP B.V.
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A current monitor includes current sense logic and a processor. The current sense logic senses inductor current at a predetermined time point during operation of a constant on-time regulator. The processor determines output current of the constant on-time regulator based on the inductor current sens
A current monitor includes current sense logic and a processor. The current sense logic senses inductor current at a predetermined time point during operation of a constant on-time regulator. The processor determines output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point. The predetermined time point corresponds to half of an on-time period of the constant on-time regulator. The output current may be determined during continuous conduction mode (CCM) or discontinuous conduction mode (DCM). During DCM mode, the processor determines the output current of the constant on-time regulator based on a skip time.
대표청구항▼
1. A current monitor, comprising: current sense logic configured to sense inductor current at a predetermined time point during operation of a constant on-time regulator; anda processor configured to determine output current of the constant on-time regulator based on the inductor current sensed at t
1. A current monitor, comprising: current sense logic configured to sense inductor current at a predetermined time point during operation of a constant on-time regulator; anda processor configured to determine output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point,wherein the predetermined time point corresponds to half of an on-time period of the constant on-time regulator;wherein the constant on-time regulator is configured to operate in a discontinuous conduction mode (DCM); andwherein the processor is configured to determine the output current by calculating an average value of the output current based on the on-time period, an off-time period, and a skip period, and the inductor current sensed at half the on-time period. 2. The current monitor of claim 1, wherein the constant on-time regulator is configured to operate in continuous conduction mode (CCM) and the output current is equal to the inductor current sensed at half the on-time period. 3. The current monitor of claim 2, wherein a transistor coupled to the inductor of the constant on-time regulator is switched on during the on-time period to generate the inductor current. 4. The current mirror of claim 1, further comprising at least one timer/counter logic that is configured to: (a) determine a number of integer periods that exist during a combined period that includes the on-time period and the off-time period;(b) determine a fraction of an integer period that exists during the combined period;(c) determine a number of integer periods that exist during the skip period; and(d) determine a fraction of the integer period that exists during the skip period,wherein the processor is configured to calculate the average value of the output current based on (a) to (d) and the inductor current sensed at half the on-time period. 5. The current mirror of claim 4, wherein the at least one timer/counter logic is configured to determine the fraction of the integer period in (b) by determining a voltage stored in a capacitor during the combined period, the voltage between an initial voltage and a timer voltage that corresponds to full integer period. 6. The current mirror of claim 4, wherein the at least one timer/counter logic is configured to determine the fraction of the integer period in (d) by determining a voltage stored in a capacitor during the skip period, the voltage between an initial voltage and a timer voltage that corresponds to full integer period. 7. The current mirror of claim 4, wherein the integer period is less than the on-time period. 8. The current mirror of claim 1, wherein the constant on-time regulator is a buck regulator or a boost regulator. 9. A method for monitoring operation of a circuit, comprising: identifying a predetermined time point for a constant on-time regulator;detecting start of an on-time period of the constant on-time regulator;sensing inductor current at the predetermined time point of the on-time period; anddetermining output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point, wherein the predetermined time point corresponds to half the on-time period and the inductor current is sensed at half the on-time period;wherein the constant on-time regulator is configured to operate in a discontinuous conduction mode (DCM); andwherein determining the output current includes calculating an average value of the output current based on the on-time period, an off-time period, and a skip period, and the inductor current sensed at half the on-time period. 10. The method of claim 9, wherein the constant on-time regulator is configured to operate in a continuous conduction mode (CCM) and the output current is equal to the inductor current sensed at half the on-time period. 11. The method of claim 10, wherein a transistor coupled to the inductor of the constant on-time regulator is switched on during the on-time period to generate the inductor current. 12. The method of claim 9, further comprising: (a) determining a number of integer periods that exist during a combined period that includes the on-time period and the off-time period;(b) determining a fraction of an integer period that exists during the combined period;(c) determining a number of integer periods that exist during the skip period;(d) determining a fraction of the integer period that exists during the skip period; and(e) calculating the average value of the output current based on (a) to (d) and the inductor current sensed at half the on-time period. 13. The method of claim 12, wherein: determining the fraction of the integer period in (b) includes determining a voltage stored in a capacitor during the combined period, the voltage between an initial voltage and a timer voltage that corresponds to full integer period. 14. The method of claim 12, wherein: determining the fraction of the integer period in (d) includes determining a voltage stored in a capacitor during the skip period, the voltage between an initial voltage and a timer voltage that corresponds to full integer period. 15. The method of claim 12, wherein the integer period is less than the on-time period. 16. The method of claim 9, wherein the constant on-time regulator is a buck regulator or a boost regulator. 17. A current monitor, comprising: current sense logic configured to sense inductor current at a predetermined time point during operation of a constant on-time regulator; anda processor configured to determine output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point,wherein the predetermined time point corresponds to any point within an on-time period of the constant on-time regulator;wherein the constant on-time regulator is configured to operate in a discontinuous conduction mode (DCM); andwherein the processor is configured to determine the output current by calculating an average value of the output current based on the on-time period, an off-time period, and a skip period, and the inductor current sensed at any point within the on-time period.
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