Abstract ▼ AI-Helper

Transmission in PON system sends receiver that data without clock. At this time a receiver needs synchronicity stability clock for precise recovery. Therefore Phase locked loop to offer high system clock and Clock / Data Recovery to extract clock from high transmission rate of data research active. ...

Transmission in PON system sends receiver that data without clock. At this time a receiver needs synchronicity stability clock for precise recovery. Therefore Phase locked loop to offer high system clock and Clock / Data Recovery to extract clock from high transmission rate of data research active. In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of 2^(7)-1, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.