Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has c...
Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator(SOI) FBFET with extremely steep switching (∼1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. Also, for given various design parameters, the performance metrics of various stacked SOI FBFET device structures are compared. The 2-/3-stack SOI FBFETs are simulated with various parameters that affect device performance (i.e., effective channel width, interval length, fin height, and fin width). Using these SOI FBFETs, we propose an inverter circuit design and verified it with mixed-mode TCAD simulation data. In addition, the device structure of the SOI FBFET is optimized to be operated in an inverter circuit. As a result of the simulation of device characteristics and circuit of SOI FBFET, the prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail.
Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator(SOI) FBFET with extremely steep switching (∼1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. Also, for given various design parameters, the performance metrics of various stacked SOI FBFET device structures are compared. The 2-/3-stack SOI FBFETs are simulated with various parameters that affect device performance (i.e., effective channel width, interval length, fin height, and fin width). Using these SOI FBFETs, we propose an inverter circuit design and verified it with mixed-mode TCAD simulation data. In addition, the device structure of the SOI FBFET is optimized to be operated in an inverter circuit. As a result of the simulation of device characteristics and circuit of SOI FBFET, the prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.