An LPC cepstrum processor for speech recognition is implemented on CMOS array process. The designed processor contains a 24-bit floating-point MAC unit to perform the correlation quickly, which occupies the majority of operations used in the algorithm, and has 22 register files to store temporary variables. For the purpose of fast operations, the floating-point MAC consists of a 3-stage pipeline and the new post-normalization shceme is proposed and applied to it. Experimental result shows that it takes approximately 266.mu.s to process 200 samples/frame at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of gates are 27,760.
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