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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.38 no.6 = no.288, 2001년, pp.390 - 397
김경환 (연세대학교 전기전자공학과) , 최창순 (연세대학교 전기전자공학과) , 김정태 (연세대학교 전기전자공학과) , 최우영 (연세대학교 전기전자공학과)
A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process...
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Y-H. Kim, S-K. Chang, S-S. Kim, J-G. Choi, S-H. Lee, D-H. Hahn and H-D. Kim, 'Characteristics of Dual Polymetal (W/WNX/Poly-Si) Gate CMOS for 0.1 ${\mu}m$ DRAM Technology,' in Ext. Abst. of Int. Conf. on SSDM, pp. 12-13, Tokyo, Japan, September 1999
H. Wakabayashi, T. Yamamoto, Y. Saito, T. Ogura M. Narihiro, K. Tsuji, T. Fukai, K. Uejima, Y. Nakahara, K. Takeuchi, Y. Ochiai, T. Mogami and T. Kunio, 'A 0.1- ${\mu}m$ CMOS Device with a 40-nm Gate Sidewall and Multilevel Interconnects for System LSI,' in Symp. on VLSI Tech., pp. 107-108, Kyoto, Japan, June 1999
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Technology Modeling Associate, Inc. : TSUPREM-4, Two-Dimensional Process Silmulation Program, Version 6.5, User's Manual, Sunnyvale, California, May 1997
J. Lyu, B-G. Park, K. Chun and J-D. Lee, 'A Novel 0.1 ${\mu}m$ MOSFET Structure with Inverted Sidewall and Recessed Channel,' IEEE Electron Device Lett., Vol. 17, No. 4, pp. 157-159, April 1996
J-H. Lee, H-C. Shin, J-J. Kim, C-B. Park and Y-J. Park, 'Partially Depleted SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the Recessed Charmel Region,' IEEE Electron Device Lett., Vol. 18, No. 5, pp. 184-186, May 1997
Technology Modeling Associate, Inc. : MEDICI, Two-Dimensional Device Simulation Program, Version 4.0, User's Manual, Sunnyvale, California, October 1997
T.Y. Chan, J. Chen, P.K. Ko and C. Hu, 'The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,' in IEDM Tech. Dig., pp. 718-721, Washington D.C., USA, December 1987
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