초록

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Abstract ▼ AI-Helper

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown cha...

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

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