Hyun, Seok-Bong
(Basic Research Laboratory, ETRI)
,
Tak, Geum-Young
(Basic Research Laboratory, ETRI)
,
Kim, Sun-Hee
(Basic Research Laboratory, ETRI)
,
Kim, Byung-Jo
(Basic Research Laboratory, ETRI)
,
Ko, Jin-Ho
(PhyChips)
,
Park, Seong-Su
(Basic Research Laboratory, ETRI)
This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), ...
This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.
This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
대상 데이터
However, we have also fabricated and tested the blocks on separate chips. The proposed receiver employs two different BBA blocks, one for BT1 and the other for BT2, while sharing most of the radio building blocks such as the RF front-end and frequency synthesizer. We call this architecture a baseband dual-path.
The transmitter consists of an anti-aliasing LPF, a quadrature up-conversion mixer, and a DA. Since the baseband modulations are performed in the digital part and the noise is not a matter of concern in the transmitter, we employ a single BBApath.
성능/효과
Table 4 summarizes the transceiver performance and compares it to the Bluetooth requirements. The experimental results show an IIP3 of -5 dBm and a sensitivity of -77 dBm when the losses from the external components are compensated. Table 5 shows the distribution of the current consumption.
참고문헌 (14)
Zargari, M., Su, D.K., Yue, C.P., Rabii, S., Weber, D., Kaczynski, B.J., Mehta, S.S., Singh, K., Mendis, S., Wooley, B.A..
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems.
IEEE journal of solid-state circuits,
vol.37,
no.12,
1688-1694.
Byun, Sangjin, Park, Chan-Hong, Song, Yongchul, Wang, Sungho, Conroy, C.S.G., Kim, Beomsup.
A low-power cmos bluetooth rf transceiver with a digital offset canceling dll-based gfsk demodulator.
IEEE journal of solid-state circuits,
vol.38,
no.10,
1609-1618.
Han, Young-Nam, Bahk, Hang-Gu, Yang, Seung-Taik.
CDMA Mobile System Overview: Introduction, Background, and System Concepts.
ETRI journal,
vol.19,
no.3,
83-97.
Kim, Cheon-Soo, Park, Min, Kim, Chung-Hwan, Yu, Hyun-Kyu, Cho, Han-Jin.
Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-band CMOS LNAs.
ETRI journal,
vol.21,
no.4,
1-8.
Crols, J., Steyaert, M.S.J..
Low-IF topologies for high-performance analog front ends of fully integrated receivers.
IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Analog and digital signal processing,
vol.45,
no.3,
269-282.
D'Andrea, A.N., Mengali, U..
Performance of a quadricorrelator driven by modulated signals.
IEEE transactions on communications,
vol.38,
no.11,
1952-1957.
Khoury, J.M..
On the design of constant settling time AGC circuits.
IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Analog and digital signal processing,
vol.45,
no.3,
283-294.
Lindfors, S., Halonen, K., Ismail, M..
A 2.7-V elliptical MOSFET-only gmC-OTA filter.
IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Analog and digital signal processing,
vol.47,
no.2,
89-95.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.