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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.41 no.3 = no.321, 2004년, pp.83 - 92
박정주 (충북대학교 정보통신공학과) , 조경록 (충북대학교 정보통신공학과)
In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and ...
K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, 'A 250-mW, 8-b, 52-M sample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,' IEEE J. Solid-State Circuits, vol. 32, pp. 312-320, Mar. 1997
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S. Limotyrakis, K. Y. Nam, and b. A. Wooley, 'Analysis and Simulation of Distortion in Folding and Interpolating A/D Converters,' IEEE Transactions on Circuits and Systems-II : Analog and Digital Signal Processing, vol. 49, No. 3, pp. 161-169, March 2002
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