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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.45 no.2 = no.368, 2008년, pp.93 - 100
안진호 (호서대학교 전자공학과) , 김홍식 (연세대학교 전기전자공학과) , 김현진 (연세대학교 전기전자공학과) , 박영호 (한국전자통신연구원 NoC 기술팀) , 강성호 (연세대학교 전기전자공학과)
In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and ...
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