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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SC, 시스템 및 제어, v.46 no.1 = no.325, 2009년, pp.63 - 67
이재환 (전북대학교 전자정보공학부) , 정항근 (전북대학교 전자정보공학부)
Current mismatch in a charge pump causes degradation in spectral purity of the phase locked loops(PLLs), such as reference spurs. The current mismatch can be reduced by increasing the output resistance of the charge pump, as in a cascoded output stage. However as the supply voltage is lowered, it is...
H. Arora, N. Klemmer, J. C. Morizio, and P. D. Wolf, 'Enhanced phase noise modeling of fractional-N frequency synthesizers,' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 379-395, Feb. 2005
W. Rhee, Bang-Sup Song, Akbar Ali, 'A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order $\Delta$ $\Sigma$ modulator,' IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1453-1460, Oct. 2000
Young-Shig Choi, Dae-Hyun Han, 'Gain- boosting charge pump for current matching in phase-locked loop' IEEE Trans. Circuits Syst. II, Express Briefs, vol. 53, no. 10, pp. 1022-1025, Oct. 2006
Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim and Suki Kim, 'Charge pump with perfect current matching characteristics in phase-locked loops,' Electronics Letters, vol. 36, pp. 1907-1908, Nov. 2000
A. Waizman, 'A delay line loop for frequency synthesis of deskewed clock,' ISSCC Digest of Technical Papers, 1994
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