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참고문헌 (6)

1. Wi, J.-S., Lee, H.-S., Lim, K., Nam, S.-W., Kim, H.-M., Park, S.-Y., Lee, J. J., Hong, C. D., Jin, S. and Kim, K.-B., "Fabrication of Si Nano-pillar Array of 1 Tera-dot/in2 by Electron Beam Patterning for Nanoimprint Mold," Small, Vol. 4, No. 12, pp. 2118-2122, 2008 

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2. Sreenivasan, S. V., Willson, C. G., Schumaker, N. E. and Resnick, D. J., "Low-cost nanostructure patterning using step and flash imprint lithography," NIST-SPIE Conference on Nanotechnology, Vol. 4608, pp. 187-194, 2001 

3. Resnick, D. J., Dauksher, W. J., Mancini, D., Nordquist, K. J., Ainley, E., Gehoski, K., Baker, J. H., Bailey, T. C., Choi, B. J., Johnson, S., Sreenivasan, S. V., Ekerdt, J. G. and Willson, C. G., "High resolution templates for step and flash imprinting lithography," Proc. SPIE, Vol. 4688, pp. 205-213, 2002 

   

4. Choi, B. J., Johnson, S., Colburn, M., Sreenivasan, S. V. and Willson, C. G., "Design of Orientation Stages for Step & Flash Imprint Lithography," PrecisionEngineering, Vol. 25, No. 3, pp. 192-204, 2001 

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5. Chou, S. Y. and Krauss, P. R., "Imprint Lithography woth sub-10nm Feature Size and High Throughput," Microelectronics Engineering, Vol. 35, No. 1-4, pp.237-240, 1997 

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6. Lee, J. J., Choi, K. B. and Kim, G. H., "Design and Analysis of the Single-Step Nanoimprinting Lithography Equipment for Sub-100nm Linewidth," Current Applied Physics, Vol. 6, No. 6, pp. 1007-1011, 2006 

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