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NTIS 바로가기신뢰성응용연구 = Journal of the applied reliability, v.10 no.1 = no.29, 2010년, pp.65 - 71
Kim, Hyun-Joo (Dept. of Information Display, Hanyang University) , Kim, Kyeong-Rok (Dept. of Nanoscale Semiconductor Engineering, Hanyang University) , Kwack, Kae-Dal (Dept. of Information Display, Hanyang University)
NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair...
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F. Hofmann et al(2005), "NVM based on FinFET device structures" Solid-State Electron. 49, 1799.
N. Gupta(2007), "Threshold voltage modeling and gate oxide thickness effect on polycrystalline silicon thin-film transistors" Physica Scripta 76, 628.
B. G. Park et al(2006), "Novel Device Structures for Charge Trap Flash Memories" IEEE Solid-State and Integrated Circuit Technology, ICSICT '06.
K. H. Kim and H. J. Lee(2006), "Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate" IEICE Trans. Electron. E89-C, 578.
J. Lee et al(2002), "High-Performance 1-Gb NAND Flash Memory With 0.12- ${\mu}m$ Technology" IEEE J. Solid-St. Circ. 37, 1502.
T. Tanaka et al(1994), "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory" J. Solid-St. Circ. 29, 1366.
K. Takeuchi et al(1998), "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories" J. Solid-St. Circ. 33, 1228.
J. Lee et al(2003), "A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications" J. Solid-St Circ. 38, 1934.
S. K. Sung et al(2006), "Fully Integrated SONOS Flash Memory Cell Array With BT (Body Tied)-FinFET Structure" IEEE Trans. Nanotechnol. 5, 174.
Y. K. Lee et al(2004), "Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process" IEEE Electr. Device Lett. 25, 317.
H. G. Kim et al(2007), "Device optimization of the FinFET having an isolated n+/p+ strapped gate" Microelectron. Eng. 84, 1656 (2007).
Y. Liu et al(2004), "A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel" IEEE Electr. Device Lett. 25, 510.
M. Ieong et al(2002), " High Performance Double-Gate Device Technology Challenges and Opportunities" IEEE Computer Society, ISQED'02.
S. J. Cho et al(2006), "Design and Optimization of Two-Bit Double-Gate Nonvolatile Memory Cell for Highly Reliable Operation" IEEE Trans. Nanotechnol. 5, 180.
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