[논문]A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems

Cho, Sang-In; Kang, Kyu-Min

doi:10.4218/etrij.10.0109.0232

A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems 원문보기

ETRI journal, v.32 no.1, 2010년, pp.1 - 10

Cho, Sang-In (Broadcasting & Telecommunications Convergence Research Laboratory, ETRI) , Kang, Kyu-Min (Broadcasting & Telecommunications Convergence Research Laboratory, ETRI)

Abstract ▼ AI-Helper

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

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가설 설정

1) The nontrivial multiplier is the conventional complex variable multiplier [12], [19].

제안 방법

We determined the internal word length of the proposed FFT processor using a fixed-point simulation with MATLAB before hardware implementation. After the word length of the proposed FFT processor was chosen, the FFT architecture was modeled in Verilog HDL and functionally verified using a ModelSim simulator. Then, the FFT architecture was synthesized with the appropriate time and area constraints using the Synopsys Design Compiler.
The proposed FFT architecture consists of butterfly units (BU1, BU2, and BU3), complex constant multipliers (CCM1, CCM2, and CCM3), complex booth multipliers (CBMs), and registers [5], [17]. As discussed in section II, the proposed FFT architecture is based on both the modified radix-24 and the radix-23 DIF FFT algorithms in order to reduce the number of multipliers. The proposed FFT architecture actually requires multipliers in three stages, namely, stages 2, 4, and 6.
To further reduce the hardware complexity and power consumption, Cho and others recently presented a four-parallel data-path 128-point mixed-radix decimation-in-frequency (DIF) FFT processor operating at over 132 MHz in [5]. In the proposed FFT processor, nontrivial complex multiplication operations are only needed at the fourth stage by breaking up the 128-point FFT algorithm into two FFT algorithms, namely, radix-24 FFT and radix-23 FFT algorithms. Because a relatively large number of constant multipliers are required to implement twiddle factors (TFs) at the end of each stage in a conventional radix-24 FFT architecture [12], a modified radix-24 FFT structure without constant multipliers at the third stage is presented.
A four-parallel data-path receiver structure including an FFT block and a Viterbi decoder can be considered to limit the system clock of the baseband modem core to a maximum of 132 MHz for practical VLSI implementation [15], [16]. In this paper, we propose a hardware-efficient 128-point mixed-radix FFT architecture with four data paths to meet the high-speed requirements. The signal flow graph of the proposed fourparallel data-path 128-point FFT processor is shown in Fig.
Figure 3 shows a block diagram of the proposed four-parallel data-path 128-point FFT processor. The proposed FFT architecture consists of butterfly units (BU1, BU2, and BU3), complex constant multipliers (CCM1, CCM2, and CCM3), complex booth multipliers (CBMs), and registers [5], [17]. As discussed in section II, the proposed FFT architecture is based on both the modified radix-24 and the radix-23 DIF FFT algorithms in order to reduce the number of multipliers.
We break up the 128-point DFT into a 16-point DFT and an 8- point DFT, where the 16-point and 8-point DFTs are implemented by applying the modified radix-24 FFT algorithm and radix-2³ FFT algorithm, respectively.

대상 데이터

One OFDM symbol in the MB-OFDM UWB system consists of 128 subcarriers and 37 zero samples. The 128 subcarriers are composed of 100 data subcarriers, 12 pilot subcarriers, 10 guard subcarriers, and 6 null subcarriers. Therefore, the fast Fourier transform (FFT) processor of the MB-OFDM UWB system conducts a 128-point FFT operation, where the sampling frequency is 528 MHz and the subcarrier frequency spacing is 4.
The proposed FFT architecture employs three kinds of butterfly units (BU1, BU2, and BU3). The butterfly units perform complex addition and complex subtraction with the two complex data inputs as shown in Figs.

이론/모형

There were also mistakes in the figures of [5]. In this paper, we present mathematical formulation and analysis of the proposed 128- point mixed-radix FFT algorithm. Detailed characteristics of the proposed FFT processor are also analyzed.
In this subsection, we further decompose the butterfly of radix-8 into three stages by adopting a radix-23 FFT algorithm. Let

참고문헌 (19)

A. Batra et al., "Design of a Multiband OFDM System for Realistic UWB Channel Environments," IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, Sept. 2004, pp. 2123-2138.

상세보기
K.M. Kang and S.S. Choi, "Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-wideband Transmission," ETRI Journal, vol. 30, no. 4, Aug. 2008, pp. 495-505.

원문보기 상세보기
W. Abbott et al., Multiband OFDM Physical Layer Specification, Version 1.2 (draft), WiMedia Alliance, Feb. 2007.
Y.W. Lin, H.Y. Liu, and C.Y. Lee, "A 1-GS/s FFT/IFFT Processor for UWB Applications," IEEE J. Solid-State Circuits, vol. 40, no. 8, Aug. 2005, pp. 1726-1735.

상세보기
S.I. Cho, K.M. Kang, and S.S. Choi, "Implementation of 128-Point Fast Fourier Transform Processor for UWB Systems," Proc. IEEE IWCMC, Aug. 2008, pp. 210-213.
J.S. Lee et al. "A High-Speed, Low-Complexity Radix- $2^4$ FFT Processor for MB-OFDM UWB Systems," Proc. IEEE ISCAS, May 2006, pp. 4719-4722.
T.S. Chakraborty and S. Chakrabarti, "A Reduced Area 1 GSPS FFT Design Using MRMDF Architecture for UWB Communication," Proc. IEEE APCCAS, Nov. 2008, pp. 1128-1131.
Z. Wang et al., "A Novel FFT Processor for OFDM UWB Systems," Proc. IEEE APCCAS, Dec. 2006, pp. 374-377.
S. Qiao et al., "An Area and Power Efficient FFT Processor for UWB Systems," Proc. IEEE WICOM, Sept. 2007, pp. 582-585.
J. Garcia, J.A. Michel, and A.M. Buron, "VLSI Configurable Delay Commutator for a Pipeline Split Radix FFT Architecture," IEEE Trans. Signal Process., vol. 47, no. 11, Nov. 1999, pp. 3098-3107.

상세보기
K. Maharatna, E. Grass, and U. Jagdhold, "A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM," IEEE J. Solid-State Circuits, vol. 39, no. 3, Mar. 2004, pp. 484-493.

상세보기
C.-P. Fan, M.-S. Lee, and G.-A. Su, "A Low Multiplier and Multiplication Costs 256-Point FFT Implementation with Simplified Radix- $2^4$ SDF Architecture," Proc. IEEE APCCAS, Dec. 2006, pp. 1935-1938.
K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, New York; John Wiley & Sons, 1999.
G. Zhong et al., "An Energy-Efficient Reconfigurable Angle-Rotator Architecture," Proc. IEEE ISCAS, vol. 3, May 2004, pp. 661-664.
C.H. Shin et al., "A Design and Performance of 4-Parallel MBOFDM UWB Receiver," IEICE Trans. Commun., vol. E90-B, no. 3, Mar. 2007, pp. 672-675.

상세보기
S.W. Choi, K.M. Kang, and S.S. Choi, "A Two-Stage Radix-4 Viterbi Decoder for Multiband OFDM UWB Systems," ETRI Journal, vol. 30, no. 6, Dec. 2008, pp. 850-852.

원문보기 상세보기
K.J. Cho et al., "Design of Low-Error Fixed-Width Modified Booth Multiplier," IEEE Trans. VLSI Syst., vol. 12, no. 5, May 2004, pp. 522-531.

상세보기
S.M. Kim, J.G. Chung, and K.K. Parhi, "Low Error Fixed-Width CSD Multiplier with Efficient Sign Extension," IEEE Trans. Circuits & Systems II, vol. 50, no. 12, Dec. 2003, pp. 984-993.

상세보기
Y. Jung, H. Yoon, and J. Kim, "New Efficient FFT Algorithm and Pipeline Implementation Results for OFDM/DMT Applications," IEEE Trans. Consumer Elect., vol. 49, no. 1, Feb. 2003, pp. 14-20.

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A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems 원문보기

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A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems 원문보기

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