[논문]Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory

Kim, Dae Hwan; Park, Sungwook; Seo, Yujeong; Kim, Tae Geun; Kim, Dong Myong; Cho, Il Hwan

doi:10.5573/jsts.2012.12.4.449

Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory 원문보기

Journal of semiconductor technology and science, v.12 no.4, 2012년, pp.449 - 457

Kim, Dae Hwan (School of Electrical Engineering , Kookmin University) , Park, Sungwook (School of Electrical Engineering , Kookmin University) , Seo, Yujeong (Department of Electronics Engineering, Korea University) , Kim, Tae Geun (Department of Electronics Engineering, Korea University) , Kim, Dong Myong (School of Electrical Engineering , Kookmin University) , Cho, Il Hwan (Department of Electronic Engineering , Myongji University)

Abstract ▼ AI-Helper

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

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제안 방법

In this work, for unified understanding, the P/E cyclic endurances of MANOS memories are comprehensively investigated in comparison with those of SONOS memories. During the P/E cycling by the FN stress, both Si/SiO₂ interface trap (N_IT) and border trap in the bottom oxide (N_OT) are characterized in detail by analyzing the P/E cycle evolution of V_T, the subthreshold swing (SSW), the hysteresis during a readout condition, and the P/E efficiency. In addition, the dynamic BTI behaviors including the temperature-dependences of both the P/E stress time-evolution and the P/E cycle-evolution of V_T and/or SSW are characterized.
Motivated by these viewpoints, we reported the dynamic bias temperature instability (BTI) behaviors of P/E cycled cell in SONOS memories [11]. In this work, for unified understanding, the P/E cyclic endurances of MANOS memories are comprehensively investigated in comparison with those of SONOS memories. During the P/E cycling by the FN stress, both Si/SiO₂ interface trap (N_IT) and border trap in the bottom oxide (N_OT) are characterized in detail by analyzing the P/E cycle evolution of V_T, the subthreshold swing (SSW), the hysteresis during a readout condition, and the P/E efficiency.

이론/모형

The SONOS CTF memories with an extremely scaled gate (L × W=30 × 30 nm 2 ) were formed by the sidewall patterning technique [12].

참고문헌 (20)

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상세보기
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상세보기
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상세보기
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Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory 원문보기

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Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory 원문보기

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