[논문]Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors

Samuel, T.S.Arun; Balamurugan, N.B.; Sibitha, S.; Saranya, R.; Vanisri, D.

doi:10.5370/jeet.2013.8.6.1481

Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors 원문보기

Journal of electrical engineering & technology, v.8 no.6, 2013년, pp.1481 - 1486

Samuel, T.S.Arun (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) , Balamurugan, N.B. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) , Sibitha, S. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) , Saranya, R. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering) , Vanisri, D. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering)

Abstract ▼ AI-Helper

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

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문제 정의

From the presented results, it can be concluded that the DMG structure provides wide range of benefits to the TFET performance. The results clearly demonstrate the excellent immunity against SCE offered by the DMG structure while decreasing channel length.

가설 설정

ie., region under metal 1. Due to this effect the tunneling current gets increased. The electric field near the drain decreases with the change in the work function.

제안 방법

The aim of this work is, to study the potential benefits offered by the DMG TFET by using parabolic approximation technique for the first time, which is simple and accurate. The analytical model is developed using two dimensional solution of Poisson equation.

대상 데이터

In order to fulfill the scaling law, various device structures are required for maintaining the device characteristics accurately. These device structures include double gate (DG) MOSFETs, dual material gate (DMG) MOSFETs, surrounding gate (SG) MOSFETs, and dual material surrounding gate (DMSG) MOSFETs device. The key factors that limit the performance of MOS devices are increased short channel effects (SCE) and very high leakage current.

이론/모형

The analytical model is based on two-dimensional Poisson’s equation which is solved by using parabolic approximation.
The aim of this work is, to study the potential benefits offered by the DMG TFET by using parabolic approximation technique for the first time, which is simple and accurate. The analytical model is developed using two dimensional solution of Poisson equation. This model is used to calculate the surface potential and electric field distribution in the device under the two metal gates and the drain current I_DS is derived from the electric field using Kane’s model.
The tunneling generation rate (G) can be calculated using Kane’s model.
This model is used to calculate the surface potential and electric field distribution in the device under the two metal gates and the drain current IDS is derived from the electric field using Kane’s model.

참고문헌 (17)

P. K.Tiwari and S. Jit, "A Subthreshold Swing Model for Symmetric Double Gate (DG) MOSFETs with Vertical Gaussian Doping", Journal of Semiconductor Technology and Science, Vol.10, No.2, pp.107-16, Jun. 2010.

원문보기 상세보기
Z. Ding, G. Hu, J. Gu, R. Liu, and L.Wang "An analytical model for the subthreshold swing of double-gate MOSFETs," International Workshop on IWJT, 2010, pp.1-4.
Q. Zhang, W. Zhao, and A. Seabaugh, "Lowsubthreshold-swing tunnel transistors," IEEE Electron Device Lett., Vol. 27, No. 4, pp. 297-300, Apr. 2006.

상세보기
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상세보기
K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high-K gate dielectric," IEEE Trans. Electron Devices, Vol. 54, No. 7, pp. 1725-1733, Jul. 2007.

상세보기
K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel band gap modulation and gate work function engineering," IEEE Trans. Electron Devices, Vol. 52, No. 5, pp. 909-917, May. 2005.

상세보기
L. Wang, E. Yu, Y. Taur and P. Asbeck, "Design of tunneling field effect transistors based on staggered hetero junctions for ultra low power applications," IEEE Electron Device Lett., Vol. 31, No. 5, pp. 431-433, May. 2010.

상세보기
O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt and D. A. Antoniadis, "Design of Tunneling Field-Effect Transisitors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol. 29, No. 9, pp- 1074-1077, Sep. 2008.

상세보기
J. Appenzeller, Y. M. Lin, J. Knoch, Z. H. Chen, and P. Avouris, "Comparing carbon nanotube transistors - The ideal choice: A novel tunneling device design," IEEE Trans. Electron Devices, Vol. 52, No. 12, pp. 2568-2576,Dec. 2005.

상세보기
K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high- k gate dielectric," IEEE Trans. Electron Devices, Vol. 54, No. 7, pp. 1725-1733, Jul. 2007.

상세보기
S. Saurabh and M. Jagadesh Kumar, "Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor," IEEE Trans. on Electron Devices, Vol. 58, No. 2, pp. 404-410, Feb. 2011.

상세보기
M.J.Lee and W.Y.Choi, "Analytical Model of a single-gate silicon-on-insulator (SOI) tunneling fieldeffect transistors (TFETs)," Solid-State Elec., Vol. 63, pp.110-114, Sep. 2011.

상세보기
C. Shen, S.-L. Ong, C.-H. Heng, G. Samudra, and Y.-C. Yeo. "A variational approach to the twodimensional nonlinear Poisson's equation for the modeling of tunneling transistors," IEEE Electron Device Lett., Vol. 29, No. 11, pp. 1252-1255, Oct. 2008.

상세보기
M.G. Bardon, H.P.Neves, R.Puers, and C.V.Hoof, "Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions", IEEE Trans., Electron Devices, Vol.57, No.4, pp. 827-34, Apr. 2010.

상세보기
A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Boosting the on-current of a nchannel nanowire tunnel field-effect transistor by source material optimization," J. Appl. Phys., Vol. 104, No. 6 pp. 064 514-1,Sep. 2008.

상세보기
E.O.Kane, "Zener tunneling in semiconductors," J.Phys. Chem.Solides, Vol. 12, No. 2, pp.181-188, Jan. 1960.

상세보기
E.O. Kane, "Theory of tunneling," J. Appl. Phys., Vol. 32, No. 1, pp. 83-91, Jan.1961.

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Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors 원문보기

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Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors 원문보기

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