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NTIS 바로가기Journal of semiconductor technology and science, v.9 no.2, 2009년, pp.110 - 116
Balamurugan, N.B. (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University) , Sankaranarayanan, K. (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University) , John, M.Fathima (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University)
The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transc...
J. T. Park, and J. P. Colinge, "Multi-gate SOI MOSFETs: device design guidelines", IEEE Tran-sactions on Electron Devices, vol. 49, no. 12, pp. 2222-2229, 2002
M. J. Kumar, A. A. Orouji, and H. Dhakad, "New Dual-Material Surrounding Gate Nanoscale MOSFET: Analytical Threshold-Voltage mode", IEEE tran¬sactions on Electron Devices, vol. 53, no. 4, pp. 920-923, 2006
D. Flandre, L. F. Ferreira, P. G. A. Jespers, and J. P. Colinge, "Modeling and Applications of Fully Depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits", Solid-State Electronics, vol. 39, no.4, pp. 455-460, 1996
K. Rajendran and G. S. Samudra, "Modeling of transconductance-to-current ratio ( $g_m/I_D$ ) analysis on double-gate SOI MOSFETs", Journal of Semi-conductor Science and Technology, vol. 15, pp. 139-144, 2000
A. Kranti, Rashmi, S. Haldar, and R. S. Gupta, "Design and Optimization of Vertical Surrounding Gate MOSFETs for Enhanced transconductance-to-current ratio ( $g_m/I_{ds}$ )", Solid-state Electronics, vol. 47, pp. 153-159, 2003
N. B. Balamurugan, K. Sankaranarayanan, P. Amutha, and M. Fathima John, "An Analytical Modeling of Threshold and Subthreshold Swing on Dual Material Surrounding Gate Nanoscale MOSFETs for high speed Wireless Communication", Journal of Semiconductor Technology and Science, vol. 8, no. 3, pp. 221-226, 2008
MEDICI 4.0 User’s Manual, Technological Modeling Associates, Palo Alto, CA, 1997
K. K. Young, "Analysis of Conduction in Fully Depleted SOI MOSFETs", IEEE transactions on Electron Devices, vol. 36, No. 3, pp. 504-506, 1989
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