[논문]Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Yoo, Gwan Min; Kim, Young Jae; Eun, Hye Rim; Kang, Hye Su; Kim, Jungjoon; Cho, Seongjae; Lee, Jung-Hee; Kang, In Man

doi:10.5573/jsts.2014.14.5.508

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors 원문보기 논문타임라인

Journal of semiconductor technology and science, v.14 no.5, 2014년, pp.508 - 517

Abstract ▼ AI-Helper

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

주제어

AI 본문요약
AI-Helper

* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.

가설 설정

According to Figs. 7(a) and (b), increase of H_fin has little effect on the change in channel electron concentration at the off-state. Therefore, increasing H_fin is a better way to achieve the lower I_off and S than controlling W_fin in the JL FinFET.

제안 방법

As the scaling of the channel length continues, the design optimization of JL FinFET with sub-10 nm gate length was also required for the purpose of investigating the electrical characteristics in ultra-short-channel device because the device was more influenced by the SCE such as the drain-induced barrier lowering (DIBL). In this study, we perform an optimal design of silicon (Si)-based junctionless fin-shaped field-effect transistor (JL FinFET) and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET) which has n⁺ / p^- / n⁺ junction structure like the conventional MOSFET in contrast with the junctionless FET. The optimized design parameters are threshold voltage (V_th), on-state current (Ion), off-state current (I_off), current ratio (I_on/I_off), and subthreshold swing (S).
of 26 nm has already been performed [7]. It made a comparison between the two devices in views of the channel mobility, the gate capacitance, and short-channel characteristics. As the scaling of the channel length continues, the design optimization of JL FinFET with sub-10 nm gate length was also required for the purpose of investigating the electrical characteristics in ultra-short-channel device because the device was more influenced by the SCE such as the drain-induced barrier lowering (DIBL).

성능/효과

The gate work-functions of bulk FinFETs have been modulated for design optimization in order to quadrate with the V_th of each devices. First, the effects of H_fin in case of JL FinFET have been demonstrated. In contrast to the results in investigating the effects of W_fin, the change in H_fin brings smaller variation of I_D than that in W_fin.

참고문헌 (22)
타임라인 바로가기

T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, and F. Boeuf, "The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance," IEEE Circuits Devices Mag., vol. 21, no. 1, pp. 16-26, Jan. 2005.

상세보기
인용구절

인용 구절

As channel length scaling of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) continues, they encounter several issues closely related with short-channel effects (SCEs) [1-4].
C. Hu, "Device challenges and opportunities," in Proc. VLSI Symp. Technol., Jun. 2004, pp. 4-5.

인용구절

인용 구절

As channel length scaling of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) continues, they encounter several issues closely related with short-channel effects (SCEs) [1-4].
S. Borkar, "Circuit techniques for subthreshold leakage avoidance, control, and tolerance," in IEDM Tech. Dig., pp. 421-424, Dec. 2004.

인용구절

인용 구절

As channel length scaling of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) continues, they encounter several issues closely related with short-channel effects (SCEs) [1-4].
P. K Sahu, S. K. Mohapatra, and K. P. Pradhan, "A Study of SCEs and Analog FOMs in GS-DGMOSFET with Lateral Asymmetric Channel Doping," J. Semicond. Technol. Sci., vol. 13, no. 6, pp. 647-654, Dec. 2013.

원문보기 상세보기 타임라인에서 보기
인용구절

인용 구절

As channel length scaling of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) continues, they encounter several issues closely related with short-channel effects (SCEs) [1-4].
J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.

상세보기
인용구절

인용 구절

Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5-9].
N. D. Akhavan, I. Ferain, P. Razavi, R. Yu, and J.-P. Colinge, "Improvement of carrier ballisticity in junctionless nanowire transistors," Appl. Phys. Lett., vol. 98, no. 10, pp. 103510-1-103510-3, Mar. 2011.

상세보기
인용구절

인용 구절

Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5-9].
R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, "Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm," IEEE Electron Device Lett., vol. 32, no. 9, pp. 1170-1172, Sep. 2011.

상세보기
인용구절

인용 구절

Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5-9].

Recently, a comparison study between fabricated JL FinFET and conventional bulk FinFET with L_gof 26 nm has already been performed [7].
S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling," IEEE Electron Device Lett., vol. 32, no. 3, pp. 261-263, Mar. 2011.

상세보기
인용구절

인용 구절

Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5-9].
J. S. Lee, S. Cho, B.-G. Park, J. S. Harris, Jr, and I. M. Kang, "Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications," J. Semicond. Technol. Sci., vol. 12, no. 2, pp. 230-239, Jun. 2012.

원문보기 상세보기 타임라인에서 보기
인용구절

인용 구절

Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5-9].
C.-H. Park, M.-D. Ko, K.-H. Kim, R.-H. Baek, C.-W. Sohn, C. K. Baek, S. Park, M. J. Deen, Y.-H. Jeong, and J.-S. Lee, "Electrical characteristics of 20-nm junctionless Si nanowire transistors," Solid-State Electron., vol. 73, no. 3, pp. 7-10, Jul. 2012.

상세보기
인용구절

인용 구절

This novel feature lets us achieve simple process flow needed for ultra-shallow source/drain junctions and low thermal budgets usually causing incomplete dopant activation after gate stack formation is eliminated [10].
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-A selfaligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.

상세보기
인용구절

인용 구절

In addition, it has higher gate controllability over the channel, which effectively suppresses SCEs and widens the channel width without loss in the foot print as we adopted the fin-shaped channel [11-15].
Y. Omura, H. Konishi, and K. Yoshimoto, "Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's," J. Semicond. Technol. Sci., vol. 8, no. 4, pp. 302-310, Dec. 2008.

원문보기 상세보기 타임라인에서 보기
인용구절

인용 구절

In addition, it has higher gate controllability over the channel, which effectively suppresses SCEs and widens the channel width without loss in the foot print as we adopted the fin-shaped channel [11-15].
I. J. Park, and C. Shin, "Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs," J. Semicond. Technol. Sci., vol. 13, no. 5, pp. 511-515, Oct. 2013.

원문보기 상세보기 타임라인에서 보기
인용구절

인용 구절

In addition, it has higher gate controllability over the channel, which effectively suppresses SCEs and widens the channel width without loss in the foot print as we adopted the fin-shaped channel [11-15].
F. Najam, S. Kim, and Y. S. Yu, "Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope," J. Semicond. Technol. Sci., vol. 13, no. 5, pp. 530-537, Oct. 2013.

원문보기 상세보기 타임라인에서 보기
인용구절

인용 구절

In addition, it has higher gate controllability over the channel, which effectively suppresses SCEs and widens the channel width without loss in the foot print as we adopted the fin-shaped channel [11-15].
B. Lakshmi and R. Srinivasan, "Effect of gate electrode work function in conventional and junctionless FinFETs," Int. J. Phys. Sci., vol. 7, no. 49, pp. 6246-6254, Dec. 2012.

인용구절

인용 구절

In addition, it has higher gate controllability over the channel, which effectively suppresses SCEs and widens the channel width without loss in the foot print as we adopted the fin-shaped channel [11-15].
SILVACO International, ATLAS User's Manual, Apr. 2012.

인용구절

인용 구절

A design optimization and device performances are presented through a three-dimensional (3-D) technology computer-aided design (TCAD) simulation tool [16].

To increase the accuracy of simulation results, multiple models including concentration-dependent mobility model, field-dependent mobility model, gate current model, and structure-dependent (2-D and 3-D) mobility model have been included in the simulations [16].
Process Integration, Devices, and Structures (PIDS) Chapter, International Technology Roadmap for Semiconductors (ITRS), 2012 edition.

인용구절

인용 구절

The drive voltage (V_DD) of 0.65 V was applied to satisfy the low standby power (LSTP) requirements in the most recent technology roadmap [17].
M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, "Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- ${\kappa}$ Gate Dielectrics," IEEE Trans. Electron Devices, vol. 56, no. 1, pp. 100-108, Jan. 2009.

상세보기
인용구절

인용 구절

V_th was defined as the gate voltage (V_GS) at drain current (I_D) = 10^-7 A/μm and it is widely known constant-current method for defining V_th in low-power devices [18].
A. Nandi, A. K. Saxena, and S. Dasgupta, "Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length," IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1529-1535, May. 2013.

상세보기
인용구절

인용 구절

The doping concentrations in the n⁺ source (N_source)/p^- channel (N_ch)/n⁺ drain (N_drain) were widely used 1.0×10²⁰ cm^-3, 1.0×10¹⁶ cm^-3, and 1.0×10²⁰ cm^-3, in sequence [19].
C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electron., vol. 54, no. 2, pp. 97-103, Feb. 2010.

상세보기
인용구절

인용 구절

Seeing that the DIBL of JL FinFET is much smaller than that of the conventional bulk FinFET, the SCEs are expected to be suppressed more effectively in the JL FinFET device [20].
S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, "RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1388-1396, May. 2011.

상세보기
인용구절

인용 구절

C_gs and C_gd are fixed by oxide and channel surface charges in these devices [21].
Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press, New York, USA, 1999, pp. 467-491, 500-504.

인용구절

인용 구절

(1) and (2) [22].

저자의 다른 논문 :

LOADING...

표제어: PCR

동의어: Packet Collision Rate

용어 설명 출처 목록 (6)

용어 설명: PCR은 세균 특이성이 있는 primer를 이용하여 적은 수의 세균이 있을지라도 쉽게 검출할 수 있는 유용한 방법이며, 이를 이용하여 구강 내 치면세균막이나 타액에서 직접 세균을 검출할 수 있게 되었다[8].

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 논문명, 저널/프로시딩명, 저자 , 발행년, 권, 호, 시작페이지, 끝페이지, 발행기관 관리번호, 논문명, 대등논문명, 저자 , 저널/프로시딩명, 발행기관, 발행년, 발행언어, 권, 호, 시작페이지, 끝페이지, ISBN, ISSN, 주제분야, 키워드, 초록(한글), 초록(영문), 저자(소속기관)
저장형식	Text(ASCII format) Excel format RefWorks Direct Export RIS format (for Reference Manager, ProCite, EndNote), Scholar's Aids, Mendeley
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증