[논문]High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

Lee, Junan; Huang, Qiwei; Kim, Kiwoon; Kim, Kyunghoon; Burm, Jinwook

doi:10.5573/jsts.2015.15.1.022

[국내논문] High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs 원문보기

Journal of semiconductor technology and science, v.15 no.1, 2015년, pp.22 - 28

Lee, Junan (Dept. of Electronic Engineering, Sogang University) , Huang, Qiwei (Dept. of Electronic Engineering, Sogang University) , Kim, Kiwoon (Dept. of Electronic Engineering, Sogang University) , Kim, Kyunghoon (Dept. of Electronic Engineering, Sogang University) , Burm, Jinwook (Dept. of Electronic Engineering, Sogang University)

Abstract ▼ AI-Helper

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

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제안 방법

A DAC based ramp generator is shared by all ADCs. The basic concept of the proposed circuit is to store the ramp value in the 1^st hold capacitor (C_H1 in Fig. 1) at the moment of changing the comparator output during the 1^st ADC step, and then using the stored value as an offset voltage of the coarse ramp signal during the 2^nd ADC step. In the 2^nd ADC step, the 2^nd ramp value are stored in the 2^nd hold capacitor (C_H2 in Fig.
The designed VGA CIS consists of a row decoder, a band- gap reference (BGR), a column multiplexer (MUX), a current DAC based single ramp generator, VGA pixels, and 640 three-step SS-ADCs. Each of the three-step SS- ADC structure was designed to allow a 12 bit A/D conversion that is composed of 6 bit, 5 bit, and 3 bit decision levels for the 1^st, 2^nd, and 3^rd conversions, respectively. To reduce the error of between steps, a digital error correction scheme (redundancy calibration) is utilized.

대상 데이터

2. The designed VGA CIS consists of a row decoder, a band- gap reference (BGR), a column multiplexer (MUX), a current DAC based single ramp generator, VGA pixels, and 640 three-step SS-ADCs. Each of the three-step SS- ADC structure was designed to allow a 12 bit A/D conversion that is composed of 6 bit, 5 bit, and 3 bit decision levels for the 1^st, 2^nd, and 3^rd conversions, respectively.

참고문헌 (9)

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상세보기
Nakamura, J., "Image Sensors and Signal Processing for Digital Still Cameras;" Taylor & Francis: London, UK, 2006; pp. 144-178.
Seunghyun Lim, Jeonghwan Lee, Dongsoo Kim and Gunhee Han, "A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs," IEEE Electron Devices, vol. 56, no. 3, March 2009, pp. 393-398.

상세보기
S. Lim, J. Cheon, S. Ham, and G. Han, "A new Correlated Double Sampling and Single slope ADC circuit for CMOS Image Sensors," in Proc. Int. SoC Des. Conf., Seoul, Korea, Oct. 2004, pp. 129-131.
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Martijn F.Snoeij, Albert J. P. Theuwissen, Kofi A. A.Makinwa, Johan H. Huijsing "Multiple Ramp Column-Parallel ADC Architectures for CMOS Image Sensors" IEEE Journal of Solid-State Circuits, vol. 42, no. 12, Dec 2007, pp. 2968-2977

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Yeonseong Hwang and Minkyu song, "Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC" Journal of semiconductor technology and science, vol. 14, no. 2, Apr 2014, pp. 246-251

원문보기 상세보기
Y. Yoshihara et al. "A 1/1.8-inch 6.4 MPixel 60frames/s CMOS Image Sensor with seamless mode change," IEEE Journal of Solid-State Circuits, vol. 41, Dec 2006, pp. 2998-3006

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