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Analysis on Self-Heating Effect in 7 nm Node Bulk FinFET Device 원문보기

Journal of semiconductor technology and science, v.16 no.2, 2016년, pp.204 - 209  

Yoo, Sung-Won (Department of Electrical and Computer Engineering and the Interuniversity Semiconductor Research Center (ISRC), Seoul National University) ,  Kim, Hyunsuk (Department of Electrical and Computer Engineering and the Interuniversity Semiconductor Research Center (ISRC), Seoul National University) ,  Kang, Myounggon (Korea National University of Transportation, Department of Electronics Engineering) ,  Shin, Hyungcheol (Department of Electrical and Computer Engineering and the Interuniversity Semiconductor Research Center (ISRC), Seoul National University)

Abstract ▼ AI-Helper 아이콘AI-Helper

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigat...

주제어

#Bulk FinFET   #self-heating effect   #thermal conductivity $R_{th}$   #lattice temperature  

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제안 방법

  • In this paper, SHE in 7 nm node non-rectangular Bulk FinFET was analyzed using 3D device simulation with consideration to contact via and pad. SHE with device parameter variation and operation temperature was compared and analyzed.
  • Substrate is determined to be the main heat transfer path through the comparison of extracted Rth value at each node. Self-heating effect with device parameter and operation temperature was analyzed. In addition, it was confirmed that the impact of interconnects connected between the device is to reduce hot spot temperature by providing the heat transfer path.

이론/모형

  • Tungsten is assumed for the material of contact via, whereas copper is assumed for contact pad. In this simulation, Hydrodynamics charge balance model was used in order to consider local lattice and carrier temperature. And, thermal boundary condition at each node (gate, source, drain, and substrate) was specified from surface resistance.
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참고문헌 (9)

  1. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, "Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures", IEEE Transactions on Electron Devices, vol. 59, pp. 1353-1363, 2012. 

    상세보기 crossref

  2. K. E. Goodson and P. Eric, "Thermal phenomena in nanoscale transistors," in Proc. Conf. Thermal Thermo Mech. Phenom. Electron. Syst., 2004, pp. 1-7. 

  3. Yang-Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, Erik Anderson, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu, "Sub-20 nm CMOS FinFET Technologies", IEEE International Electron Device Meeting (IEDM), pp. 421-424, 2001. 

  4. C.C. Wu et al., "High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme", IEEE IEDM Tech. Dig., pp. 600-603, 2010. 

  5. W. Molzer, Th. Schulz, W. Xiong, R. C. Cleavelin, K. Schrufer, A. Marshall, K. Matthews, J. Sedlmeir, D. Siprak, G. Knoblinger, L. Bertolissi, P. Patruno, and J.-P. Colinge, "Self-Heating Simulation of Multi-Gate FETs", Proceeding of European Solid-State Device Conference, pp. 311-314, 2006. 

  6. Fiegna, C., Yang Yang, Sangiorgi, E., O'Neill, and Anthony G., "Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation", IEEE Transactions on Electron Devices , vol. 55, pp. 233-244, 2008. 

    상세보기 crossref

  7. Tsunaki Takahashi, Nobuyasu Beppu, Kunro Chen, Shunri Oda, and Ken Uchida, "Self-Heating Effects and Analog Performance Optimization of Fin-type Field-Effect Transistors", Japanese Journal of Applied Physics, vol, 52, no.4, pp. CC031-CC037, 2013. 

  8. Tsunaki Takahashi, Shunri Oda, and Ken Uchida, "Methodology for Evaluating Operation Temperatures of Fin-Type Field-Effect Transistors Connected by Interconnect Wires", Japanese Journal of Applied Physics, vol, 52, pp. 42031-42037, 2013. 

  9. Tsunaki Takahashi, Nobuyasu Beppu, Kunro Chen, Shunri Oda, and Ken Uchida, "Thermal-Aware Device Design of Nanoscale Bulk/SOI FinFETs: Suppression of Operation Temperature and Its Variability", IEEE International Electron Device Meeting, pp. 809-812, 2011. 

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