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[국내논문] General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors 원문보기

Journal of information and communication convergence engineering, v.14 no.2, 2016년, pp.115 - 121  

Najam, Syed Faraz (Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia) ,  Tan, Michael Loong Peng (Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia) ,  Yu, Yun Seop (Department of Electrical, Electronic, and Control Engineering and IITC, Hankyong National University)

Abstract ▼ AI-Helper 아이콘AI-Helper

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented...

Keyword

#Compact model   #Drain current   #Inverter   #Potential profile   #TFET   #Verilog  

AI 본문요약
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제안 방법

  • This lack of a concise modeling approach integrating all of the above mentioned issues impedes development of SPICE models for TFETs. In this work, we devise a clear double-gate (DG) TFET modeling approach and use it to develop a DGTFET Verilog-A model implemented in SPICE.
  • (11) and (12) were used to develop the SPICE model for the DGTFET, and are a very important component of the SPICE model. While only 2 dielectric constants were considered in this work, the procedure presented in this work is general and could be used to develop SPICE models for any combination of DGTFET device parameters mentioned in Table 1.

데이터처리

  • Using the fitting equations, a DGTFET SPICE model was developed. SPICE simulation results were presented for the DGTFET. By finding relevant Ak/Bk fits, the procedure presented in this work could be used to expand the current SPICE model to any combination of DGTFET structural parameters.
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참고문헌 (19)

  1. ITRS report [Online], Available: http://www.itrs2.net/itrsreports.html. 

  2. Universal TFET model [Online], Available: https://nanohub.org/publications/31/1. 

  3. III-V Tunnel FET Model [Online], Available: https://nanohub.org/publications/12/2. 

  4. A. Biswas, L. De Michielis, A. Bazigos, and A. M. Ionescu, "Compact modeling of DG-Tunnel FET for Verilog-A implementation," in Proceeding of 2015 45th European Solid State Device Research Conference (ESSDERC), Graz, pp. 40-43, 2015. 

  5. C. Tanaka, K. Adachi, M. Fujimatsu, Y. Kondo, A. Hokazono, and S. Kawanaka, “Implementation of TFET SPICE model for ultra-low power circuit analysis,” IEEE Journal of the Electron Devices Society, 2016, http://dx.doi.org.10.1109/JEDS.2016.2550606. 

    상세보기 crossref

  6. M. G. Bardon, H. P. Neves, R. Puers, and C. Van Hoof, “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions,” IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 827-834, 2010. 

    상세보기 crossref

  7. A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis, “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1674-1680, 2009. 

    상세보기 crossref

  8. L. Zhang, J. He, and M. Chan, "A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors," in Proceeding of 2012 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 1-4, 2012. 

  9. R. Vishnoi and M. J. Kumar, “Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport,” IEEE Transactions on Electron Devices, vol. 61, no. 6, pp. 1936-1942, 2014. 

    상세보기 crossref

  10. J. Wan, C. Le Royer, A. Zaslavsky, and A. Cristoloveanu, “A tunneling field effect transistor model combining interband tunneling with channel transport,” Journal of Applied Physics, vol. 110, no. 10, article ID. 104503, 2011. 

    상세보기 crossref

  11. H. Xu, Y. Dai, N. Li, and J. Xu, “A 2-D semi-analytical model of double-gate tunnel field-effect transistor,” Journal of Semiconductors, vol. 36, no. 5, pp. 1-7, 2015. 

  12. J. Wang, C. Wu. Q. Huang, C. Wang, and R. Huang, “A closedform capacitance model for tunnel FETs with explicit surface potential solutions,” Journal of Applied Physics, vol. 116, no. 9, article ID. 094501, 2014. 

    상세보기

  13. M. Gholizadeh and S. E. Hosseini, “A 2-D analytical model for double-gate tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1494-1500, 2014. 

    상세보기 crossref

  14. V. Prabhat and A. K. Dutta, “Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2190-2196, 2016. 

    상세보기 crossref

  15. L. Zhang, X. Lin, J. He, and M. Chan, “An analytical charge model for double-gate tunnel FETs,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp. 3217-3223, 2012. 

    상세보기 crossref

  16. C. Wu, R. Huang, Q. Huang, C. Wang, J. Wang, and Y. Wang, “An analytical surface potential model accounting for the dualmodulation effects in tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2690-2696, 2014. 

    상세보기 crossref

  17. E. O. Kane, “Zener tunneling in semiconductors,” Journal of Physics and Chemistry of Solids, vol. 12, no. 2, pp. 181-188, 1960. 

    상세보기 crossref

  18. C. Wang, C. Wu, J. Wang, Q. Huang, and R. Huang, “Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling,” Science China Information Sciences, vol. 58, no. 2, pp. 1-8, 2015. 

    상세보기

  19. SILVACO International, ATLAS II Framework (ver. 5.10.2.R), Santa Clara, CA, 2005. 

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