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Si1-xGex Positive Feedback Field-effect Transistor with Steep Subthreshold Swing for Low-voltage Operation 원문보기

Journal of semiconductor technology and science, v.17 no.2, 2017년, pp.216 - 222  

Hwang, Sungmin (Department of Electrical and Computer Engineering, Seoul National University) ,  Kim, Hyungjin (Department of Electrical and Computer Engineering, Seoul National University) ,  Kwon, Dae Woong (Department of Electrical and Computer Engineering, Seoul National University) ,  Lee, Jong-Ho (Department of Electrical and Computer Engineering, Seoul National University) ,  Park, Byung-Gook (Department of Electrical and Computer Engineering, Seoul National University)

Abstract ▼ AI-Helper 아이콘AI-Helper

The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injec...

주제어

#Low power devices   #steep subthreshold slope   #positive feedback   #field-effect transistor  

AI 본문요약
AI-Helper 아이콘 AI-Helper

* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.

제안 방법

  • The advantage of this structure is that the programming bias scheme can become simple because it only needs to trap one type of carriers for the feedback operation. In order to estimate the accurate electrical characteristics of the proposed device, SentaurusTM TCAD simulator of Synopsys Inc. (ver. K-2015.06-SP1) was used, and the detailed parameters of simulated device are summarized in Table 1.

대상 데이터

  • 1. The device is a double-gated structure with one-sided nitride spacer and asymmetrically doped n+ source and p+ drain regions. The doping concentration of source and drain regions is 1021 cm-3.
본문요약 정보가 도움이 되었나요?

참고문헌 (21)

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    상세보기 crossref

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    상세보기 crossref

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    상세보기 crossref

  5. H. Kim, and B.-G. Park, "A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure," Journal of the Korean Physical Society, Vol. 69, No. 3, pp. 323-327, Aug. 2016. 

    상세보기 crossref

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    상세보기 crossref

  7. D. W. Kwon, J. H. Kim, E. Park, J. Lee, T. Park, R. Lee, S. Kim, and B.-G. Park, "Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain," Japanese Journal of Applied Physics, Vol. 55, No. 6S1, pp. 06GG04-1-06GG04-4, Jun. 2016. 

    상세보기 crossref

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    상세보기 crossref

  9. J. H. Kim, S. W. Kim, H. W. Kim, and B.-G. Park, "Vertical type double gate tunnelling FETs with thin tunnel barrier," Electronics Lett., Vol. 51, No. 9, pp. 718-720, Apr. 2015. 

    상세보기 crossref

  10. P.-Y. Wang and B.-Y. Tsui, "Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio," IEEE Electron Device Lett., Vol. 36, No. 12, Dec. 2015. 

    상세보기

  11. C. Wu, R. Huang, Q. Huang, J. Wang, and Y. Wang, "Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior," IEEE Electron Device Lett., Vol. 37, No. 1, Jan. 2016. 

    상세보기

  12. P. Long, J. Z. Huang, M. Povolotskyi, G. Klimeck, and M. J. W. Rodwell, "High-Current Tunneling FETs With (110) Orientation and a Channel Heterojunction," IEEE Electron Device Lett., Vol. 37, No. 3, Mar. 2016. 

  13. F. J. Garcia-Sanchez, A. Ortiz-Conde, J. Muci, and A. S. Gonzalez, "Systematic Characterization of Tunnel FETs Using a Universal Compact Model," IEEE Trans. on Electron Devices, Vol. 62, No. 11, Nov. 2015. 

  14. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "Impact ionization MOS (I-MOS)-Part I: device and circuit simulations," IEEE Trans. Electron Devices, Vol. 52, No. 1, pp. 69-76, Jan. 2005. 

    상세보기 crossref

  15. M. J. Kumar, M. Maheedhar, and P. P. Varma, "Bipolar I-MOS-An Impact-Ionization MOS With Reduced Operating Voltage Using the Open-Base BJT Configuration," IEEE Trans. on Electron Devices, Vol. 62, No. 12, Dec. 2015. 

  16. S. Ramaswamy and M. J. Kumar, "Junctionless Impact Ionization MOS: Proposal and Investigation," IEEE Trans. on Electron Devices, Vol. 61, No. 12, Dec. 2014. 

  17. A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T-S. K. Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages," IEEE Int. Electron Devices Meeting Tech. Dig., pp. 1-4, Dec. 2008. 

  18. C. W. Yeung, A. Padilla, T-S. K. Liu, and C. Hu, "Programming Characteristics of the Steep Turn-on/off Feedback FET (FBFET)," Symposium on VLSI Technology, pp. 176-177, 2009. 

  19. Y. Jeon, M. Kim, D. Lim, and S. Kim, "Steep Subthreshold Swing n-and p-Channel Operation of Bendable Feedback Field-Effect Transistors with $p^+-i-n^+$ Nanowires by Dual-Top-Gate Voltage Modulation," Nano Lett., Vol. 15, No. 8, pp.4905-4913, July. 2015. 

    상세보기 crossref

  20. Y. Taur and T. H. Ning, "Fundamentals of modern VLSI devices," Cambridge university press, 2009. 

  21. M. E. Levinshtein, S. L. Rumyantsev, and M. S. Shur, "Properties of Advanced Semiconductor Materials GaN, AlN, InN, BN, SiC, SiGe," John Wiley & Sons, Inc., 2001. 

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