Braganca, Wagno Alves Junior
(Department of Advanced Device Technology, University of Science and Technology)
,
Eom, Yong-Sung
(ICT Materials and Components Laboratory, ETRI)
,
Jang, Keon-Soo
(Department of Chemical and Materials Engineering (Polymer), The University of Suwon)
,
Moon, Seok Hwan
(ICT Materials and Components Laboratory, ETRI)
,
Bae, Hyun-Cheol
(ICT Materials and Components Laboratory, ETRI)
,
Choi, Kwang-Seong
(Department of Advanced Device Technology, University of Science and Technology)
Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each ...
Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.
Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.
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문제 정의
This paper investigated the single‐tier LAB process for 3D TSV integration with NCP to establish a process window for reliable collective LAB integration. The basic principles of light‐solid material interaction (reflection, transmission, and absorption) and the heat generation mechanisms for the LAB process were reviewed.
제안 방법
Eight bare silicon samples with thicknesses of 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, and 400 μm were prepared for the absorbance measurement.
The present research aims at establishing a LAB process window for collective 3D TSV integration with NCP, in which several TSV chips are integrated simultaneously. This novel process is expected to increase the productivity while maintaining the reliability of the solder joints.
대상 데이터
The samples were polished from the backside to the respective thicknesses. A PerkinElmer Lambda 750 UV/Vis/NIR Spectrometer was used for the measurements. The wavelength spectrum was set from 200 nm to 2,000 nm with increments of 5 nm.
The test vehicle consists of six tiers of silicon chips stacked onto a silicon substrate. The dimensions (l × w × t) of the chip and substrate are 3 × 3 × 0.
성능/효과
[11] developed and reported a LAB process for 3D TSV integration using a proprietary nonconductive paste (NCP) material [12]. They concluded that the NCP material behaves as expected during the LAB process, simultaneously acting as both a flux and an underfill, with a total process time of less than 10 s.
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