[논문]배터리 전류의 정밀 측정을 위한 단일 비트 2차 CIFF 구조 델타 시그마 모듈레이터

배기경; 천지민

doi:10.17661/jkiiect.2020.13.3.184

배터리 전류의 정밀 측정을 위한 단일 비트 2차 CIFF 구조 델타 시그마 모듈레이터
A Single-Bit 2nd-Order CIFF Delta-Sigma Modulator for Precision Measurement of Battery Current 원문보기

한국정보전자통신기술학회논문지 = Journal of Korea institute of information, electronics, and communication technology, v.13 no.3, 2020년, pp.184 - 196

배기경 (R&D Center, PIXELPLUS) , 천지민 (School of Electronic Engineering, Kumoh National Institute of Technology)

초록
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본 논문에서는 배터리 관리 시스템 (BMS)에서 2차 전지 배터리를 통해 흐르는 전류의 정밀한 측정을 위한 cascaded-of-integrator feedforward (CIFF) 구조의 단일 비트 2차 델타-시그마 모듈레이터를 제안하였다. 제안된 모듈레이터는 2개의 스위치드 커패시터 적분기, 단일 비트 비교기, 비중첩 클록 발생기 및 바이어스와 같은 주변 회로로 구현하였다. 제안된 구조는 낮은 공통 모드 입력 전압을 가지는 low-side 전류 측정 방법에 적용되도록 설계되었다. Low-side 전류 측정 방법을 사용하면 회로 설계에 부담이 줄어들게 되는 장점을 가진다. 그리고 ±30mV 입력 전압을 15비트 해상도를 가지는 ADC로 분해하기 때문에 추가적인 programmable gain amplifier (PGA)를 구현할 필요가 없어 수 mW의 전력소모를 줄일 수 있다. 제안된 단일 비트 2차 CIFF 델타-시그마 모듈레이터는 350nm CMOS 공정으로 구현하였으며 5kHz 대역폭에 대해 400의 oversampling ratio (OSR)로 95.46dB의 signal-to-noise-and-distortion ratio (SNDR), 96.01dB의 spurious-free dynamic range (SFDR) 및 15.56비트의 effective-number-of-bits (ENOB)을 달성하였다. 델타 시그마 모듈레이터의 면적 및 전력 소비는 각각 670×490㎛2 및 414㎼이다.

Abstract ▼ AI-Helper

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

주제어

표/그림 (20)

그림 Fig. 2. Current sensing system with a shunt resistor
그림 Fig. 1. Sensor interface circuit for current measurement with a shunt resistor in the BMS
그림 Fig. 3. Current sensing methods with a shunt resistor (a) high-side sensing (b) low-side sensing
그림 Fig. 4. MATLAB Simulink Block diagram for the behavioral simulation of the proposed single-bit 2nd-order CIFF delta-sigma modulator
그림 Fig. 5. Histograms of the outputs of (a) the first integrator and (b) the second integrator
그림 Fig. 6. SNDR graph according to input magnitude of the proposed modulator
그림 Fig. 7. Circuit diagram of the proposed single-bit 2nd-order CIFF delta-sigma modulator
표 Table 1. SNDR and ENOB according to DC gain of each stage in the proposed modulator
그림 Fig. 8. OTA for the integrator of 1st-stage (a) PMOS input folded cascode OTA circuit (b) dynamic CMFB circuit
그림 Fig. 9. Frequency response of the OTA for the 1st-stage integrator
표 Table 2. Corner post-simulation results of the OTA for the 1st-stage integrator
그림 Fig. 10. OTA for the integrator of 2nd-stage
그림 Fig. 11. Frequency response of the OTA for the 2nd-stage integrator
표 Table 3. Corner post-simulation results of the OTA for the 2nd-stage integrator
그림 Fig. 12. Dynamic regenerative comparator
그림 Fig. 13. Circuit diagram of the clock generator for non-overlapping clocks
그림 Fig. 14. Microphotograph of the proposed delta-sigma modulator chip
그림 Fig. 15. Spectral response of the output signal of the proposed delta-sigma modulator under TT corner with post-simulation
표 Table 4. Corner post-simulation results
표 Table 5. Characteristics of the implemented single-bit 2nd-order delta-sigma modulator under TT corner

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제안 방법

In this paper, we consider the design of the sensor interface circuit to measure the current precisely among the parameters such as voltage, temperature, and current to check the battery operation. In general, there are two measurement techniques for measuring current.
In this paper, we proposed the single-bit 2nd-order delta-sigma modulator with the architecture of CIFF for precision measurement of current flowing through the secondary cell battery in the BMS. The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit.
The method is divided into a high-side sensing method with a shunt resistor between the battery and the system and a low-side sensing method with a shunt resistor between the system and ground.
7 shows the proposed single-bit 2nd-order CIFF delta-sigma modulator to achieve high resolution. The proposed delta-sigma modulator circuit is composed of two switched-capacitor integrators, a clock generator, a single bit comparator, and other logic for control and digital signal output.
In this paper, we proposed the single-bit 2nd-order delta-sigma modulator with the architecture of CIFF for precision measurement of current flowing through the secondary cell battery in the BMS. The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage.
The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design.
9 shows the frequency responses obtained by performing the post-simulations with parasitic effects on the OTA for the first integrator. The simulations are performed under TT corner, FF corner, and SS corner.Table 2 shows the corner post-simulation results of the OTA.

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