Abstract ▼ AI-Helper

Abstract In order to increase the machine protection of KSTAR, it is more important than ever to generate an event to turn off the related heating devices even when the abnormal situation occurs during the plasma discharge. KSTAR has built the Fast Interlock System (FIS) since achieving first plasm...

Abstract In order to increase the machine protection of KSTAR, it is more important than ever to generate an event to turn off the related heating devices even when the abnormal situation occurs during the plasma discharge. KSTAR has built the Fast Interlock System (FIS) since achieving first plasma in 2008, and built and operated the 4th version of FIS which using NI c-RIO technology in 2018 []. We moved the machine protection related functionalities such as heating stop, soft-landing, and etc. of the Central Control System (CCS) built on the existing Versa module Europa bus (VME) to FIS []. The EPICS IRIO driver [] enables complete control and monitoring of the Field Programmable Gate Array (FPGA), and the distributed interlock information can be integrated in the FIS Input Output Controller (IOC) via Experimental Physics and Industrial Control System (EPICS) []. Hardwired signals processed by FPGA are connected to each of dedicated systems, and informational signal is published and subscribed by EPICS. The FIS Operator Interface (OPI) panel is developed using Control System Studio (CSS), an operator can easily understand the FIS operation status and the KSTAR shot progress status at a glance. It displays the event occurrence and sequence status on the screen, records event occurrences in the log file, and makes possible to operate with minimal operator’s intervention. The FPGA, which is responsible for signal processing at high speed, implements the event counter logic to record the event occurrence time. The counter values are synchronized with the Central Timing Unit (CTU) start time and show relative time from shot start. The event generated in the FPGA is displayed in 10 microseconds resolution by the 100 kHz operation period. In case of abnormality, generating the fast interlock is the most important function of the fast interlock system. In this paper we will describe the detail implementation and operation results.

Keyword