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NTIS 바로가기IEEE transactions on electron devices, v.69 no.4, 2022년, pp.2088 - 2093
Kim, Soyoun (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea) , Lee, Kitae (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea) , Kim, Sihyun (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea) , Kim, Munhyeon (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea) , Lee, Jong-Ho (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea) , Kim, Sangwan (Department of Electronic Engineering, Sogang University, Seoul, Republic of Korea) , Park, Byung-Gook (Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea)
초록이 없습니다.
Where are my Gaa-Fets TSMC to Stay With Finfet for 3 nm Cutress 2020
Samsung at Foundry Event Talks About 3 nm, MBCFET Developments Cohen 2019
TSMC Plots an Aggressive Course for 3 nm Lithography and Beyond Hruska 2020
Samsung Foundry 3 nm Gate All Around Process Node, 3GAE, Delayed to as Late as 2024 Patel 2021
IEDM Tech. Dig. 3 nm GAA technology featuring multi-bridge-channel fet for low power and high performance applications Bae 28.7.1
IEEE Symp. VLSI Technol. Conf., Short Course Breaking the limitations of the FinFET scalings Liu
Oldiges, Phil, Vega, Reinaldo A., Utomo, Henry K., Lanzillo, Nick A., Wassick, Thomas, Li, Juntao, Wang, Junli, Shahidi, Ghavam G.. Chip Power-Frequency Scaling in 10/7nm Node. IEEE access : practical research, open solutions, vol.8, 154329-154337.
Nagy, Daniel, Indalecio, Guillermo, GarcíA-Loureiro, Antonio J., Elmessary, Muhammad A., Kalna, Karol, Seoane, Natalia. FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability. IEEE journal of the Electron Devices Society, vol.6, 332-340.
Sentaurus Device 2019
Thirunavukkarasu, Vasanthan, Yi-Ruei Jhan, Yan-Bo Liu, Yung-Chun Wu. Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.36, no.7, 645-647.
Sachid, Angada B., Huang, Yao-Min, Chen, Yi-Ju, Chen, Chun-Chi, Lu, Darsen D., Chen, Min-Cheng, Hu, Chenming. FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.38, no.1, 16-19.
Cheng, Kangguo, Park, Chanro, Wu, Heng, Li, Juntao, Nguyen, Son, Zhang, Jingyun, Wang, Miaomiao, Mehta, Sanjay, Liu, Zuoguang, Conti, Richard, Loubet, Nicolas J., Frougier, Julien, Greene, Andrew, Yamashita, Tenko, Haran, Balasubramanian, Divakaruni, Rama. Improved Air Spacer for Highly Scaled CMOS Technology. IEEE transactions on electron devices, vol.67, no.12, 5355-5361.
Proc. Symp. VLSI Technol. Super low-power advanced 5 nm extended platform technology for extreme low voltage applications Choi 1
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