참고문헌 (39)

1. Auth 2017 2017 IEEE International Electron Devices Meeting (IEDM) A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects 

2. Yu 251 2002 Digest. International Electron Devices Meeting FinFET scaling to 10 nm gate length 

3. IEEE Trans. Electron. Dev. Yoon 67 1 258 2019 10.1109/TED.2019.2951671 Sensitivity of source/drain critical dimension variations for sub-5-nm node fin and nanosheet FETs 

   상세보기

4. IEEE Trans. Electron. Dev. Wu 52 1 63 2004 Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET 

5. Tripathi 1 2012 2012 2nd International Conference on Power, Control and Embedded Systems Characteristic comparison of connected DG FINFET, TG FINFET and Independent Gate FINFET on 32 nm technology 

6. Microelectron. Eng. Poljak 86 10 2078 2009 10.1016/j.mee.2009.01.066 Improving bulk FinFET DC performance in comparison to SOI FinFET 

   상세보기

7. J. Comput. Electron. Maity 18 2 492 2019 10.1007/s10825-018-01294-z Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation 

   상세보기

8. Jang 11 2015 2015 IEEE International Electron Devices Meeting (IEDM) Self-heating on bulk FinFET from 14nm down to 7nm node 

9. Chang 2F 2015 2015 IEEE International Reliability Physics Symposium Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects 

10. Bae 2018 2018 IEEE International Electron Devices Meeting (IEDM) 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications 

11. J. Vac. Sci. Technol. B Nanotechnol. Microelectron.: Mater. Process. Meas. Phenom. Ding 39 1 2021 Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects 

12. Bangsaruntip 20 2013 2013 IEEE International Electron Devices Meeting Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond 

13. IEEE Trans. Electron. Dev. Jung 69 3 930 2022 10.1109/TED.2022.3143473 Analytical model of contact resistance in vertically stacked nanosheet FETs for Sub-3-nm technology node 

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14. IEEE Trans. Electron. Dev. Sung 67 9 3504 2020 10.1109/TED.2020.3007134 Fabrication of vertically stacked nanosheet junctionless field-effect transistors and applications for the CMOS and CFET inverters 

    상세보기

15. IEEE Trans. Electron. Dev. Kim 67 6 2648 2020 10.1109/TED.2020.2989416 Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs 

    상세보기

16. Hon 1 2018 2018 China Semiconductor Technology International Conference (CSTIC) Simulation for the feasibility of high-mobility channel in 3D nand memory 

17. Siddique 213 2018 2018 10th International Conference on Electrical and Computer Engineering (ICECE) Physical understanding on the interface states and grain boundary defects of polysilicon nanowires 

18. Sol. Energy Mater. Sol. Cell. Baier 130 124 2014 10.1016/j.solmat.2014.07.002 Properties of electronic potential barriers at grain boundaries in Cu (In, Ga) Se2 thin films 

    상세보기

19. Semicond. Sci. Technol. Kim 30 8 2015 10.1088/0268-1242/30/8/085015 Three-dimensional simulation of threshold voltage variations due to an oblique single grain boundary in sub-40 nm polysilicon nanowire FETs 

    상세보기

20. Ahn 55 2020 2020 IEEE Silicon Nanoelectronics Workshop (SNW) Superior subthreshold slope of gate-all-around (GAA) p-type poly-Si junctionless nanowire transistors with highly suppressed grain boundary defects 

21. Phys. Scripta Gupta 71 2 225 2005 10.1238/Physica.Regular.071a00225 An analytical model of the influence of grain size on the mobility and transfer characteristics of polysilicon thin-film transistors (TFTs) 

    상세보기

22. Proc. IEEE Grasser 91 2 251 2003 10.1109/JPROC.2002.808150 A review of hydrodynamic and energy-transport models for semiconductor device simulation 

    상세보기

23. Synopsys 2016 Device User Guide, Version L-2016.03 

24. IEEE Trans. Electron. Dev. Penzin 64 11 4599 2017 10.1109/TED.2017.2751968 Kinetic velocity model to account for ballistic effects in the drift-diffusion transport approach 

    상세보기

25. Solid State Electron. Slotboom 20 4 279 1977 10.1016/0038-1101(77)90108-3 The pn-product in silicon 

    상세보기

26. J. Appl. Phys. Persson 86 8 4419 1999 10.1063/1.371380 Band gap narrowing in n-type and p-type 3C-, 2H-, 4H-, 6H-SiC, and Si 

    상세보기

27. Solid State Electron. Klaassen 35 2 125 1992 10.1016/0038-1101(92)90051-D Unified apparent bandgap narrowing in n-and p-type silicon 

    상세보기

28. Yoon 903 1999 Proceedings of the IEEK Conference The study on the implementation of philips unified mobility 

29. SIAM J. Appl. Math. Poupaud 50 6 1593 1990 10.1137/0150094 On a system of nonlinear Boltzmann equations of semiconductor physics 

    상세보기

30. Carroll 2007 Investigation of the Hurkx Model for Simualtion of Trap-Assisted Tunneling in Narrow Band Semiconductor Diodes 

31. Goetzberger vol. 1 1998 

32. IEEE Electron. Device Lett. Seo 40 4 566 2019 10.1109/LED.2019.2901003 Fabrication and characterization of a thin-body poly-Si 1T DRAM with charge-trap effect 

    상세보기

33. IEEE Access Park 9 163675 2021 10.1109/ACCESS.2021.3133572 Design of capacitorless DRAM based on polycrystalline silicon nanotube structure 

    상세보기

34. IEEE Access Lee 9 50281 2021 10.1109/ACCESS.2021.3068987 Polycrystalline-silicon-MOSFET-based capacitorless DRAM with grain boundaries and its performances 

    상세보기

35. Wang 2009 Electronic Design Automation: Synthesis, Verification, and Test 

36. IEEE Access Jeong 8 35873 2020 10.1109/ACCESS.2020.2975017 Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application 

    상세보기

37. IEEE Trans. Electron. Dev. Yoon 66 4 1868 2019 10.1109/TED.2019.2897873 Metal source-/drain-induced performance boosting of sub-7-nm node nanosheet FETs 

    상세보기

38. Taur 172 2009 Fundamentals of Modern VLSI Devices 

39. IEEE Access Yoon 7 38593 2019 10.1109/ACCESS.2019.2904944 Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain 

    상세보기

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