최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기IEEE journal of solid-state circuits, v.23 no.5, 1988년, pp.1241 - 1248
Katoozi, M. (Seattle Silicon Corp., Bellevue, WA, USA) , Soma, M.
A testable design of a CMOS synchronous counter is presented with test vectors that provide 100% coverage of stuck-at and stuck-open faults in a time of order L2, where L is the bit length of the counter. This design is made compatible with the scan design methodology by incurring minimal hardware overhead which is also fully testable for the above faults. Test application time is shown to be strongly dependent on observability of the counter outputs and can be considerably reduced if the outputs are directly observable without having to scan the test results out. The authors develop a signal flow model for the counter, based on which, test vectors are derived and proved to provide complete coverage of the above faults. The design is also superior in that its operating speed is only limited by a single inverter delay, found to be 1-4 ns per bit slice, depending on the CMOS process. Furthermore, this speed is not affected by the addition of scan circuitry.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.