[논문]A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Ju-Ho Sohn; Jeong-Ho Woo; Min-Wuk Lee; Hye-Jung Kim; Woo, R.; Hoi-Jun Yoo

doi:10.1109/JSSC.2006.872869

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

IEEE journal of solid-state circuits, v.41 no.5, 2006년, pp.1081 - 1091

Ju-Ho Sohn (Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea) , Jeong-Ho Woo (Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea) , Min-Wuk Lee , Hye-Jung Kim , Woo, R. , Hoi-Jun Yoo

Abstract ▼ AI-Helper

A 36 mm2 graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-μm 6-metal standard CMOS logic process.

참고문헌 (18)

10.1145/383259.383274
10.1109/ISSCC.2005.1493934
10.1145/1058129.1058144
Woo, Ramchan, Choi, Sungdae, Sohn, Ju-Ho, Song, Seong-Jun, Yoo, Hoi-Jun. A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. IEEE journal of solid-state circuits, vol.39, no.2, 358-367.

상세보기
0
Proc HotChips 10 sa1500: a300 mhz risc cpu with attached media processor gandhi 1998
Suzuoki, M., Kutaragi, K., Hiroi, T., Magoshi, H., Okamoto, S., Oka, M., Ohba, A., Yamamoto, Y., Furuhashi, M., Tanaka, M., Yutaka, T., Okada, T., Nagamatsu, M., Urakawa, Y., Funyu, M., Kunimatsu, A., Goto, H., Hashimoto, K., Ide, N., Murakami, H., Ohtaguro, Y., Aono, A.. A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. IEEE journal of solid-state circuits, vol.34, no.11, 1608-1618.

상세보기
Game Developers Conf 3-d graphics optimization for arm architecture kolli 2002
Woo, Ramchan, Yoon, Chi-Weon, Kook, Jeonghoon, Lee, Se-Joong, Yoo, Hoi-Jun. A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. IEEE journal of solid-state circuits, vol.37, no.10, 1352-1355.

상세보기
Woo, Ramchan, Choi, Sungdae, Sohn, Ju-Ho, Song, Seong-Jun, Yoo, Hoi-Jun. A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. IEEE journal of solid-state circuits, vol.39, no.2, 358-367.

상세보기
10.1109/ISSCC.2001.912578
10.1109/ISSCC.2004.1332730
10.1109/ISSCC.2004.1332729
Clark, D.. Mobile processors begin to grow up. Computer, vol.35, no.3, 22-25.

상세보기
Proc Siggraph/Eurographics Workshop on Graphics Hardware 3-d lsi core for mobile phonez3d kameyama 2003 60
10.1109/ISSCC.2000.839762
Hashimoto, T., Ohashi, M., Matsuo, M., Kuromaru, S., Mori-iwa, T., Hamada, M., Sugisawa, Y., Tomita, H., Hoshino, M., Nakamura, T., Ishida, K., Watada, K., Fukunaga, T., Michiyama, J.. A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications. IEEE journal of solid-state circuits, vol.37, no.11, 1574-1581.

상세보기
Akenine-Möller, Tomas, Ström, Jacob. Graphics for the masses : a hardware rasterization architecture for mobile phones. ACM transactions on graphics, vol.22, no.3, 801-808.

상세보기

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 논문명, 저널/프로시딩명, 저자 , 발행년, 권, 호, 시작페이지, 끝페이지, 발행기관 관리번호, 논문명, 대등논문명, 저자 , 저널/프로시딩명, 발행기관, 발행년, 발행언어, 권, 호, 시작페이지, 끝페이지, ISBN, ISSN, 주제분야, 키워드, 초록(한글), 초록(영문), 저자(소속기관)
저장형식	Text(ASCII format) Excel format RefWorks Direct Export RIS format (for Reference Manager, ProCite, EndNote), Scholar's Aids, Mendeley
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Abstract ▼ AI-Helper

참고문헌 (18)

이 논문을 인용한 문헌

관련 콘텐츠

원문 URL 링크

이 논문과 함께 이용한 콘텐츠

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트