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Abstract ▼ AI-Helper

In this paper, we have presents a modified clock gating block which is transformed from the previous clock gating block using ODC(Observability Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL) and applied practically to conventional micro...

In this paper, we have presents a modified clock gating block which is transformed from the previous clock gating block using ODC(Observability Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL) and applied practically to conventional micro-processor for low power design. Our modified clock gating block can be more reduced the power dissipation since it controls the clock in a bit of the register blocks comparing to the previous clock gating block. The presented clock gating block also applied to the register block which have a lot of power dissipation and the data bus blocks, ALU block, other several blocks additionally. Experimental results shows that our clock gating method more reduces dynamic power dissipations of around 46% comparing to those of the results of experiment which is not used ODC computation.

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