참고문헌 (47)

1. Solid-State Electronics Kim 53 792 2009 10.1016/j.sse.2009.03.019 Floating gate technology for high performance 8-level 3-bit NAND flash memory 

   상세보기

2. IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) Yun 26 247 2009 Various flash memory devices of novel design 

3. 10.1117/12.814258 M.C. Smayling, V. Axelrad, 32nm and below logic patterning using optimized illumination and double patterning, in: Proceedings of SPIE - The International Society for Optical Engineering, San Jose, CA, 2009. 

   

4. Proceedings of the IEEE Micheloni 97 148 2009 10.1109/JPROC.2008.2007477 Non-volatile memories for removable media 

   상세보기

5. IEEE Journal of Solid-State Circuits Park 44 208 2009 10.1109/JSSC.2008.2006437 A fully performance compatible 45 nm 4-gigabit three dimensional double-stacked multi-level NAND flash memory with shared bit-line structure 

   상세보기

6. 10.1109/IEDM.2008.4796601 S. Lai, Non-volatile memory technologies: the quest for ever lower cost, in: Technical Digest - International Electron Devices Meeting, IEDM, San Francisco, CA, 2008. 

   

7. C.Y. Lu, T.C. Lu, R. Liu, Non-volatile memory technology - today and tomorrow, in: Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, 2006, pp. 18-23. 

8. Microelectronic Engineering Lu 86 283 2009 10.1016/j.mee.2008.08.007 Future challenges of flash memory technologies 

   상세보기

9. 10.1109/IEDM.2008.4796830 A.J. Walker, Sub-50nm DG-TFT-SONOS - the ideal flash memory for monolithic 3-D integration, in: Technical Digest - International Electron Devices Meeting, IEDM, San Francisco, CA, 2008. 

   

10. Solid-State Electronics Kakoschke 52 550 2008 10.1016/j.sse.2008.01.003 Use of Al2O3 as inter-poly dielectric in a production proven 130nm embedded flash technology 

    상세보기

11. IEEE Electron Device Letters Shim 29 512 2008 10.1109/LED.2008.920979 Sonos-type flash memory cell with metal/Al2O3/SiN/ Si3N4/Si structure for low-voltage high-speed program/erase operation 

    상세보기

12. 10.1109/NVMT.2007.4389937 D.S. Golubovi, M. Boutchich, N. Akil, M.J. Van Duuren, Advanced high-K/metal gate charge trapping memories for post-45nm node, in: Proceedings - 2007 Non-volatile Memory Technology Symposium, NVMTS 07, Albuquerque, NM, 2007, pp. 15-19. 

    

13. IEEE Electron Device Letters Padovani 30 882 2009 10.1109/LED.2009.2024622 Modeling TANOS memory program transients to investigate charge-trapping dynamics 

    상세보기

14. IEEE Electron Device Letters Goel 30 216 2009 10.1109/LED.2009.2012397 Erase and retention improvements in charge trap flash through engineered charge storage layer 

    상세보기

15. 10.1109/NVSMW.2008.45 G. Van Den Bosch, A. Furnmont, M.B. Zahid, R. Degraeve, L. Breuil, A. Cacciato, A. Rothschild, C. Olsen, U. Ganguly, J. Van Houdt, Nitride engineering for improved erase performance and retention of TANOS NAND flash memory, in: 2008 Joint Non-volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD, Opio, 2008, pp. 128-129. 

    

16. 10.1109/VTSA.2008.4530795 Y.N. Tan, H.C. Wen, C. Park, D.C. Gilmer, C.D. Young, D. Heh, P. Sivasubramani, J. Huang, P. Majhi, P.D. Kirsch, B.H. Lee, H.H. Tseng, R. Jammy, Tunnel oxide dipole engineering in TANOS flash memory for fast programming with good retention and endurance, in: International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, 2008, pp. 54-55. 

    

17. 10.1109/RELPHY.2008.4558919 C. Sandhya, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S.M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, S. Mahapatra, Nitride engineering and the effect of interfaces on Charge Trap flash performance and reliability, in: IEEE International Reliability Physics Symposium Proceedings, Phoenix, AZ, 2008, pp. 406-411. 

    

18. 10.1109/VLSIT.2007.4339758 Z. Huo, J. Yang, S. Lim, S. Baik, J. Lee, J. Han, I.S. Yeo, U.I. Chung, L.T. Moon, B.I. Ryu, Band engineered charge trap layer for highly reliable MLC flash memory, in: Digest of Technical Papers - Symposium on VLSI Technology, Kyoto, 2007, pp. 138-139. 

    

19. 10.1109/IEDM.2007.4419100 T.A. Hsu, H.T. Lue, E.K. Lai, J.Y. Hsieh, S.Y. Wang, L.W. Yang, Y.C. King, T. Yang, K.C. Chen, K.Y. Hsieh, R. Liu, C.Y. Lu, A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of finFET, in: Technical Digest - International Electron Devices Meeting, IEDM, Washington, DC, 2007, pp. 913-916. 

    

20. IEEE Transactions on Electron Devices Wang 54 2699 2007 10.1109/TED.2007.904396 Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer 

    상세보기

21. 10.1109/RELPHY.2007.369887 C. Kang, J. Choi, J. Sim, C. Lee, Y. Shin, J. Park, J. Sel, S. Jeon, Y. Park, K. Kim, Effects of lateral charge spreading on the reliability of TANOS (TaN/AIO/SiN/Oxide/Si) NAND flash memory, in: Annual Proceedings - Reliability Physics (Symposium), Phoenix, AZ, 2007, pp. 167-170. 

    

22. Nature Nanotechnology Lee 2 790 2007 10.1038/nnano.2007.380 Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties 

    상세보기

23. 10.1109/IMW.2009.5090594 D.C. Gilmer, N. Goel, H. Park, C. Park, J. Barnett, P.D. Kirsch, R. Jammy, High work-function oxygen-bearing electrodes for improved performance in MANOS charge-trap NVM and MIM-DRAM type devices, in Memory Workshop, 2009. IMW ‘09. IEEE International, 2009, pp. 1-2. 

    

24. Applied Surface Science Robertson 190 2 2002 10.1016/S0169-4332(01)00832-7 Band structures and band offsets of high K dielectrics on Si 

    상세보기

25. Journal of Vacuum Science Technology - Part B Robertson 18 1785 2000 10.1116/1.591472 Band offsets of wide-band-gap oxides and implications for future electronic devices 

    상세보기

26. 10.1557/PROC-592-87 J. Robertson, E. Riassi, J.P. Maria, A.I. Kingon, Band alignments of high-k dielectrics on Si and Pt, in: Materials Research Society Symposium - Proceedings, vol. 592, 2000, pp. 87-92. 

    상세보기

27. Microelectronic Engineering Govoreanu 86 1807 2009 10.1016/j.mee.2009.03.099 Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate flash memory 

    상세보기

28. Microelectronic Engineering Ielmini 86 1870 2009 10.1016/j.mee.2009.03.054 Reliability issues and modeling of flash and post-flash memory 

    상세보기

29. 10.1109/ICSICT.2006.306465 R. Huang, F. Zhou, Y. Li, Y. Cai, X. Shan, X. Zhang, Y. Wang, Novel silicon-based flash cell structures for low power and high density memory applications, in: ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, Shanghai, 2007, pp. 709-712. 

    

30. 10.1109/IEDM.2007.4418971 G. Molas, M. Bocquet, J. Buckley, J.P. Colonna, L. Masarotto, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, P. Brianceau, L. Vermande, P. Scheiblin, A.M. Papon, G. Auvert, L. Perniola, C. Licitra, T. Veyron, N. Rochat, C. Bongiorno, S. Lombardo, B. De Salvo, S. Deleonibus, Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node flash NAND applications, in: Technical Digest - International Electron Devices Meeting, IEDM, Washington, DC, 2007, pp. 453-456. 

    

31. H.T. Lue, S.Y. Wang, E.K. Lai, Y.H. Shih, S.C. Lai, L.W. Yang, K.C. Chen, J. Ku, K.Y. Hsieh, R. Liu, C.Y. Lu, BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability, in: Technical Digest - International Electron Devices Meeting, IEDM, Washington, DC, MD, 2005, pp. 547-550. 

32. IEEE Electron Device Letters Govoreanu 24 99 2003 10.1109/LED.2002.807694 Variot: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices 

    상세보기

33. 10.1109/RELPHY.2006.251327 C.C. Yeh, Y.Y. Liao, T. Wang, W.J. Tsai, T.C. Lu, H.L. Kao, T.F. Ou, M.S. Chen, Y.J. Chen, E.K. Lai, Y.H. Shih, W. Ting, Y.H.J. Ku, C.Y. Lu, Insight of stress effect on the ONO stack layer in a SONOS-type flash memory cell, in: IEEE International Reliability Physics Symposium Proceedings, San Jose, CA, 2006, pp. 691-692. 

    

34. S. Kim, S.J. Baik, Z. Huo, Y.J. Noh, C. Kim, J.H. Han, I.S. Yeo, U.I. Chung, J.T. Moon, B.I. Ryu, Robust multi-bit programmable flash memory using a resonant tunnel barrier, in: Technical Digest - International Electron Devices Meeting, IEDM, Washington, DC, MD, 2005, pp. 861-864. 

35. 10.1109/VTSA.2009.5159337 D.C. Gilmer, N. Goel, S. Verma, H. Park, C. Park, G. Bersuker, P.D. Kirsch, K.C. Saraswat, R. Jammy, Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance, in: VLSI Technology, Systems, and Applications, 2009. VLSI-TSA ‘09. International Symposium on 2009, pp. 156-157. 

    

36. IEEE Electron Device Letters Melde 30 568 2009 10.1109/LED.2009.2017497 Select device disturb phenomenon in TANOS NAND flash memories 

    상세보기

37. 10.1109/NVSMW.2008.40 S.I. Chang, C.H. Lee, C. Kang, S. Jeon, J. Kim, B.I. Choi, Y. Park, J. Park, W. Jeong, J. You, B. Choi, J. Sel, S.S. Jae, Y. Shin, J. Choi, W.S. Lee, Reliability characteristics of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory with rounded corner (RC) structure, in: 2008 Joint Non-volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD, Opio, 2008, pp. 117-118. 

    

38. 10.1109/NVMT.2008.4731201 T. Melde, M.F. Beug, L. Bach, S. Riedel, N. Chan, C. Ludwig, T. Mikolajick, Accurate program simulation of TANOS charge trapping devices, in: Proceedings - 2008 9th Annual Non-volatile Memory Technology Symposium, NVMTS 2008, Pacific Grove, CA, 2008. 

    

39. IEEE Transactions on Device and Materials Reliability Babu 7 420 2007 10.1109/TDMR.2007.907295 Electrical and reliability studies of “wet N2O” tunnel oxides grown on silicon for flash memory applications 

    상세보기

40. H.P. Belgal, N. Righos, I. Kalastirsky, J.J. Peterson, R. Shiner, N. Mielke, A new reliability model for post-cycling charge retention of flash memories, in: Annual Proceedings - Reliability Physics (Symposium), Dallas, TX, 2002, pp. 7-20. 

41. 10.1149/1.2209257 P. Blomme, B. Govoreanu, M. Rosmeulen, A. Akheyar, L. Haspeslagh, J. De Vos, M. Lorenzini, J. Van Houdt, K. De Meyer, High-k materials for tunnel barrier engineering in floating-gate flash memories, in: Meeting Abstracts, Los Angeles, CA, 2005, p. 973. 

    상세보기

42. 10.1109/VTSA.2006.251054 C.H. Chen, P.Y. Chiang, S.S. Chung, T. Chen, G.C.W. Chou, C.H. Chu, Understanding of the leakage components and its correlation to the oxide scaling on the SONOS cell endurance and retention, in: International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, 2006, pp. 34-35. 

    

43. Tamkang Journal of Science and Engineering Chen 7 161 2004 A study on tunneling current of ONO films and data retention effects in flash memories 

    상세보기

44. H.H. Tseng, P.J. Tobin, E.A. Hebert, S. Kalpat, M.E. Ramon, L. Fonseca, Z.X. Jiang, J.K. Schaeffer, R.I. Hegde, D.H. Triyoso, D.C. Gilmer, W.J. Taylor, C.C. Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, B.W. Chan, A. Haggag, S. Backer, R. Noble, M. Jahanbani, Y.H. Chiu, B.E. White, Defect passivation with fluorine in a TaxCy/high-k gate stack for enhanced device threshold voltage stability and performance, in: Technical Digest - International Electron Devices Meeting, IEDM, 2005, pp. 696-699. 

45. IEEE Transactions on Electron Devices Tseng 54 3267 2007 10.1109/TED.2007.908897 Defect passivation with fluorine and interface engineering for Hf-based high-k/metal gate stack device reliability and performance enhancement 

    상세보기

46. 10.1109/IMW.2009.5090575 S. Verma, G. Bersuker, D.C. Gilmer, A. Padovani, P. Hokyung, A. Nainani, D. Heh, J. Huang, J. Jiang, K. Parat, P.D. Kirsch, L. Larcher, T. Hsing-Huang, K.C. Saraswat, R. Jammy, A novel fluorine incorporated band engineered (BE) tunnel (SiO2/HfSiO/SiO2) TANOS with excellent program/erase & endurance to 105 Cycles, in: Memory Workshop, 2009. IMW ‘09. IEEE International, 2009, pp. 1-2. 

    

47. 10.1109/VTSA.2007.378899 H.T. Lue, S.Y. Wang, E.K. Lai, K.Y. Hsieh, R. Liu, C.Y. Lu, ABE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory, in: International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, 2007.