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NTIS 바로가기Electronics letters, v.48 no.18, 2012년, pp.1102 - 1104
Yoo, T. (Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea) , Cho, S.-J (Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea) , Lee, J. W. (Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea) , Baek, K.-H (Sch. of Electr. & Electron. Eng., Chung-Ang Univ., Seoul, South Korea)
Presented is a phase accumulator (PACC) for current-mode logic (CML)-based high-speed CMOS direct digital frequency synthesisers (DDFSs). The proposed PACC not only consumes low power by using an adaptive power reduction technique, but also updates frequency information within one clock period by us...
Yeoh, Hong Chang, Jung, Jae-Hun, Jung, Yun-Hwan, Baek, Kwang-Hyun. A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS. IEEE journal of solid-state circuits, vol.45, no.9, 1845-1855.
Thompson, M.. Low-latency, high-speed numerically controlled oscillator using progression-of-states technique. IEEE journal of solid-state circuits, vol.27, no.1, 113-117.
Yang, Byung-Do, Choi, J.-H., Han, Seon-Ho, Kim, Lee-Sup, Yu, Hyun-Kyu. An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. IEEE journal of solid-state circuits, vol.39, no.5, 761-774.
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