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NTIS 바로가기Journal of semiconductor technology and science, v.17 no.3, 2017년, pp.370 - 377
Jeong, Hocheol (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) , Kang, Jaehyun (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) , Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University) , Lee, Minjae (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST))
This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture proces...
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A. Tanabe, et al, " $0.18-{\mu}m$ CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 988-996, Jun. 2001.
P. Heydari and R. Mohanavelu, "Design of ultrahigh-speed low-voltage CMOS CML buffers and latches," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, no. 10, pp.1081-1093, Oct. 2004.
M. M. Green and U. Singh, "Design of CMOS CML circuits for high-speed broadband communications," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, pp. II-204-II-207 vol.2
H. Wang, M. Miranda,W. Dehaene, F. Catthoor, and K. Maex, "Systematic analysis of energy and delay impact of very deep submicron variability effects in embedded SRAM modules," in Proc. Design and Test in Europe (DATE) Conf., Mar. 2005, pp. 914-919.
M. Alioto and G. Palumbo, "Design strategies for source coupled logic gates," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., v vol. 50, no. 5, pp. 640-654, May 2003.
S. Bruma, "Impact of on-chip process variations MCML performance," in Proc. IEEE Int. Syst.-on-Chip Conf., Sept. 2003, pp. 135-140.
M. Alioto, et al, "Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.54, no.9, pp.1916,1928, Sept. 2007.
J. Lohstroh, "Static and dynamic noise margins of logic circuits," IEEE J, Solid-State Circuits, vol.14, no. 3, pp. 591-598, Jun. 1979.
J. Lohstroh, E. Seevinck, and J. De Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. SSC-18, no. 6, pp. 803-807, Dec. 1983.
L. Ding and P. Mazumder, "Dynamic noise margin: Definitions and model," in Proc. 17th Int. Conf. VLSI Design, 2004, pp. 1001-1006.
M. Lee, "A 20GHz variability-aware robust, high-speed and low-power MOS CML latch." IEICE Electronics Express, vol. 9, no. 14, pp. 1214-1220, July 2012.
B. Razavi, Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001, pp. 101-134.
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