참고문헌 (9)

1. Poulton, John, Palmer, Robert, Fuller, Andrew M., Greer, Trey, Eyles, John, Dally, William J., Horowitz, Mark. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. IEEE journal of solid-state circuits, vol.42, no.12, 2745-2757.

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2. Fukuda, Koji, Yamashita, Hiroki, Ono, Goichi, Nemoto, Ryo, Suzuki, Eiichi, Masuda, Noboru, Takemoto, Takashi, Yuki, Fumio, Saito, Tatsuya. A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE journal of solid-state circuits, vol.45, no.12, 2838-2849.

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3. Proc IEEE Int Solid-State Circuits Conf Tech Dig A 0.1-fref BW 1 GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering jee 2011 94 

4. Proc IEEE ISSCC Tech Dig A highly digital 0.5-to-4 Gb/s 1.9 mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS inti 2011 152 

5. Balamurugan, Ganesh, Kennedy, Joseph, Banerjee, Gaurab, Jaussi, James E., Mansuri, Mozhgan, O'Mahony, Frank, Casper, Bryan, Mooney, Randy. A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS. IEEE journal of solid-state circuits, vol.43, no.4, 1010-1019.

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6. Proc IEEE Int Solid-State Circuits Conf Tech Dig A 4.5 mW/Gb/s 6.4 Gb/s 22 $+$ 1-lane source-synchronous link RX core with optional cleanup PLL in 65 nm CMOS reutemann 2010 160 

7. Proc IEEE Int Solid-State Circuits Conf A 47 $\times$ 10 Gb/s 1.4 mW(/Gb/s) parallel interface in 45 nm CMOS o'mahony 2010 156 

8. Agrawal, A., Liu, A., Hanumolu, P.K., Gu-Yeon Wei. An 8 $\,\times\,$ 5 Gb/s Parallel Receiver With Collaborative Timing Recovery. IEEE journal of solid-state circuits, vol.44, no.11, 3120-3130.

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9. Proc IEEE VLSI Symp Circuits A 16-Gb/s differential I/O cell with 380 fs RJ in an emulated 40 nm DRAM process nguyen 2008 128