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NTIS 바로가기IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, v.60 no.2, 2013년, pp.91 - 95
Seon-Kyoo Lee (Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Byungsub Kim (Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Hong-June Park (Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea) , Jae-Yoon Sim (Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea)
This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator ...
Poulton, John, Palmer, Robert, Fuller, Andrew M., Greer, Trey, Eyles, John, Dally, William J., Horowitz, Mark. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. IEEE journal of solid-state circuits, vol.42, no.12, 2745-2757.
Fukuda, Koji, Yamashita, Hiroki, Ono, Goichi, Nemoto, Ryo, Suzuki, Eiichi, Masuda, Noboru, Takemoto, Takashi, Yuki, Fumio, Saito, Tatsuya. A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE journal of solid-state circuits, vol.45, no.12, 2838-2849.
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Agrawal, A., Liu, A., Hanumolu, P.K., Gu-Yeon Wei.
An 8
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