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The Scientific World Journal, v.2015, 2015년, pp.729165 -
Begam, V. M. Thoulath (Department of ICE, Anna University, Chennai 600 025, India) , Baulkani, S. (Department of ECE, Government College of Engineering, Tirunelveli 627 002, India)
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In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting t...
1 Kilic H. Oktem L. Low-power test pattern generator design for BIST via non-uniform cellular automata Proceedings of the IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT ’05) April 2005 213 216 10.1109/VDAT.2005.1500058
2 Zorian Y. A distributed BIST control scheme for complex VLSI devices Proceedings of the 11 Annual IEEE VLSI Test Symposium April 1993 Atlantic City, NJ, USA IEEE 4 9 10.1109/VTEST.1993.313316
3 He R. Li X. Gong Y. A low power BIST TPG design Proceedings of the IEEE 5th International ASIC Conference October 2003 Beijing, China 1136 1139 10.1109/icasic.2003.1277414
4 Wang Z. Chakrabarty K. Test data compression for IP embedded cores using selective encoding of scan slices Proceedings of the IEEE International Test Conference (ITC '05) November 2005 581 590 10.1109/test.2005.1584019 2-s2.0-33748483365
5 Gonciari P. T. Al-Hashimi B. M. Nicolici N. Variable-length input huffman coding for system-on-a-chip test IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2003 22 6 783 796 10.1109/TCAD.2003.811451 2-s2.0-0038718528
6 Ja C. K. Ismail Y. Thermal-aware methodology for repeater insertion in low-power VLSI circuits IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2007 15 8 963 970 10.1109/tvlsi.2007.900749 2-s2.0-34547468846
7 Lien W.-C. Lee K.-J. Hsieh T.-Y. Ang W.-L. An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2013 32 8 1254 1264 10.1109/tcad.2013.2253155 2-s2.0-84880910614
8 Zhou B. Ye Y.-Z. Li Z.-L. Wu X.-C. Ke R. A new low power test pattern generator using a variable-length ring counter Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED '09) March 2009 248 252 10.1109/isqed.2009.4810302 2-s2.0-67649639130
9 Li L. Chakrabarty K. Hybrid BIST based on repeating sequences and cluster analysis Proceedings of the Design, Automation and Test in Europe (DATE ’05) March 2005 1142 1147 10.1109/DATE.2005.177 2-s2.0-33646897620
10 Zhou B. Ye Y.-Z. Wang Y.-S. Simultaneous reduction in test data volume and test time for TRC-reseeding Proceedings of the 17th Great Lakes Symposium on VLSI (GLSVLSI '07) March 2007 ACM 49 54 10.1145/1228784.1228802 2-s2.0-34748815541
11 Das S. R. Sudarma M. Assaf M. H. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets IEEE Transactions on Instrumentation and Measurement 2003 52 5 1363 1380 10.1109/tim.2003.818547 2-s2.0-0242636492
12 Chakrabarty K. Murray B. T. Iyengar V. Built-in test pattern generation for high-performance circuits using twisted-ring counters Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99) April 1999 Dana Point, Calif, USA IEEE 22 27 10.1109/VTEST.1999.766642
13 Chakrabarty K. Murray B. T. Iyengar V. Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2000 8 5 633 636 10.1109/92.894170 2-s2.0-0034289979
14 Chakrabarty K. Swaminathan S. Built-in self testing of high-performance circuits using twisted-ring counters Proceedings of the IEEE Internaitonal Symposium on Circuits and Systems May 2000 72 75 2-s2.0-0033685326
15 Nourani M. Tehranipoor M. Ahmed N. Low-transition test pattern generation for BIST-based applications IEEE Transactions on Computers 2008 57 3 303 315 10.1109/tc.2007.70794 MR2418420 2-s2.0-43049136926
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